5秒后页面跳转
9DB801BG PDF预览

9DB801BG

更新时间: 2024-09-17 20:49:19
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
18页 173K
描述
Clock Driver, PDSO48

9DB801BG 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliant风险等级:5.92
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
湿度敏感等级:1端子数量:48
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源:3.3 V
认证状态:Not Qualified子类别:Clock Drivers
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUALBase Number Matches:1

9DB801BG 数据手册

 浏览型号9DB801BG的Datasheet PDF文件第2页浏览型号9DB801BG的Datasheet PDF文件第3页浏览型号9DB801BG的Datasheet PDF文件第4页浏览型号9DB801BG的Datasheet PDF文件第5页浏览型号9DB801BG的Datasheet PDF文件第6页浏览型号9DB801BG的Datasheet PDF文件第7页 
Integrated  
Circuit  
ICS9DB801  
Systems, Inc.  
Eight Output Differential Buffer for PCI Express (50-200MHz)  
Recommended Application:  
Pin Configurations  
DB800 Version 2.0 Yellow Cover part with PCI Express  
suppor with extended bypass mode frequency range.  
SRC_DIV#  
VDD  
1
2
48 VDDA  
47 GNDA  
GND  
3
4
5
6
7
8
9
10  
11  
12  
13  
46  
IREF  
Output Features:  
SRC_IN  
SRC_IN#  
OE_0  
45 LOCK  
44 OE_7  
43 OE_4  
8 - 0.7V current-mode differential output pairs  
Supports zero delay buffer mode and fanout mode  
Bandwidth programming available  
42  
41  
40  
OE_3  
DIF_7  
DIF_7#  
OE_INV  
DIF_0  
DIF_0#  
GND  
VDD  
DIF_1  
DIF_1#  
OE_1 14  
OE_2 15  
DIF_2  
DIF_2#  
GND  
VDD  
Key Specifications:  
39 VDD  
38  
37  
DIF_6  
DIF_6#  
Outputs cycle-cycle jitter < 50ps  
Outputs skew: 50ps  
50 - 200MHz operation  
Extended frequency range in bypass mode:  
Revision B: up tp 333.33 MHz  
Revision C: up to 400 MHz  
36 OE_6  
35 OE_5  
34  
33  
DIF_5  
DIF_5#  
16  
17  
18  
19  
20  
21  
22  
23  
24  
32 GND  
31 VDD  
30  
29  
DIF_4  
DIF_4#  
Features/Benefits:  
DIF_3  
DIF_3#  
28 HIGH_BW#  
27 SRC_STOP#  
26 PD#  
Spread spectrum modulation tolerant, 0 to -0.5% down  
spread and +/- 0.25% center spread.  
BYPASS#/PLL  
SCLK  
Supports undriven differential outputs in PD# and  
SRC_STOP# modes for power management.  
25 GND  
SDATA  
OE_INV = 0  
Supports polarity inversion to the output enables ,  
SRC_STOP and PD.  
SRC_DIV#  
VDD  
1
2
48 VDDA  
47 GNDA  
GND  
3
4
5
6
7
8
9
10  
11  
12  
13  
46  
IREF  
Polarity Inversion Pin List Table  
SRC_IN  
SRC_IN#  
OE0#  
45 LOCK  
44 OE7#  
43 OE4#  
OE_INV  
Pins  
6
0
OE_0  
1
OE0#  
OE3#  
OE1#  
OE2#  
PD  
42  
41  
40  
OE3#  
DIF_7  
DIF_7#  
OE_INV  
7
OE_3  
DIF_0  
DIF_0#  
GND  
VDD  
DIF_1  
DIF_1#  
OE1# 14  
OE2# 15  
DIF_2  
DIF_2#  
GND  
VDD  
14  
15  
26  
27  
35  
36  
43  
44  
OE_1  
39 VDD  
OE_2  
38  
37  
DIF_6  
DIF_6#  
PD#  
SRC_STOP#  
OE_5  
SRC_STOP  
OE5#  
OE6#  
OE4#  
OE7#  
36 OE6#  
35 OE5#  
OE_6  
34  
33  
DIF_5  
DIF_5#  
OE_4  
16  
17  
18  
19  
20  
21  
22  
23  
24  
OE_7  
32 GND  
31 VDD  
30  
29  
DIF_4  
DIF_4#  
DIF_3  
DIF_3#  
28 HIGH_BW#  
27 SRC_STOP  
26 PD  
BYPASS#/PLL  
SCLK  
25 GND  
SDATA  
OE_INV = 1  
48-pin SSOP & TSSOP  
1015B—09/07/06  

与9DB801BG相关器件

型号 品牌 获取价格 描述 数据表
9DB801GLFT IDT

获取价格

Clock Driver, PDSO48
9DB801GT IDT

获取价格

Clock Driver, PDSO48
9DB803 RENESAS

获取价格

8-output Differential Buffer for PCIe Gen2
9DB803DF IDT

获取价格

PLL Based Clock Driver, 9DB Series, 16 True Output(s), 0 Inverted Output(s), PDSO48, MO-11
9DB803DFT IDT

获取价格

PLL Based Clock Driver, 9DB Series, 8 True Output(s), 0 Inverted Output(s), PDSO48, MO-118
9DB803DG IDT

获取价格

PLL Based Clock Driver, 9DB Series, 16 True Output(s), 0 Inverted Output(s), PDSO48, 0.240
9DB803DGT IDT

获取价格

PLL Based Clock Driver, 9DB Series, 8 True Output(s), 0 Inverted Output(s), PDSO48, 6.10 M
9DB833 RENESAS

获取价格

8-output 3.3 V PCIe Gen1-2-3 Zero Delay / Fanout Buffer
9DB833AFLIFT IDT

获取价格

PLL Based Clock Driver, 9DB Series, 8 True Output(s), 0 Inverted Output(s), PDSO48, 0.300
9DB833AGLIFT IDT

获取价格

PLL Based Clock Driver, 9DB Series, 8 True Output(s), 0 Inverted Output(s), PDSO48, 6.10 M