Datasheet > 9DBL02

9DBL02

更新时间： 2022-02-26 11:00:07

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	300K
描述
2-output 3.3V PCIe Zero-Delay Buffer

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9DBL02 数据手册

2-output 3.3V PCIe Zero-Delay Buffer

9DBL02

DATASHEET

Description

Features/Benefits

The 9DBL02 devices are 3.3V members of IDT's

Full-Featured PCIe family. The devices support PCIe Gen1-4

Common Clocked (CC) and PCIe Gen2 Separate Reference

Independent Spread (SRIS) systems. It offers a choice of

integrated output terminations providing direct connection to

85 or 100 transmission lines. The 9DBL02P1 can be

factory programmed with a user-defined power up default

SMBus configuration.

• Direct connection to 100 (xx42) or 85 (xx52)

transmission lines; saves 8 resistors compared to standard

PCIe devices

• 100mW typical power consumption in PLL mode; minimal

power consumption

• SMBus-selectable features allows optimization to customer

requirements:

– control input polarity

– control input pull up/downs

– slew rate for each output

Recommended Application

PCIe Gen1-4 clock distribution for Riser Cards, Storage,

Networking, JBOD, Communications, Access Points

– differential output amplitude

– output impedance for each output

– 50, 100, 125MHz operating frequency

Output Features

• 2 – 1-200 MHz Low-Power (LP) HCSL DIF pairs

• 9DBL0242 default ZOUT = 100

• 9DBL0252 default ZOUT = 85

• 9DBL02P2 factory programmable defaults

• Easy AC-coupling to other logic families, see IDT

application note AN-891

• Customer defined SMBus power up default can be

programmed into P1 device; allows exact optimization to

customer requirements

• OE# pins; support DIF power management

• HCSL-compatible differential input; can be driven by

common clock sources

• Spread Spectrum tolerant; allows reduction of EMI

• Pin/SMBus selectable PLL bandwidth and PLL Bypass;

minimize phase jitter for each application

Key Specifications

• PCIe Gen1-2-3-4 CC compliant in ZDB mode

• PCIe Gen2 SRIS compliant in ZDB mode

• Supports PCIe Gen2-3 SRIS in fan-out mode

• DIF cycle-to-cycle jitter <50ps

• DIF output-to-output skew < 50ps

• Bypass mode additive phase jitter is 0 ps typical rms for

PCIe

• Outputs blocked until PLL is locked; clean system start-up

• Device contains default configuration; SMBus interface not

required for device operation

• Three selectable SMBus addresses; multiple devices can

easily share an SMBus segment

• Space saving 24-pin 4x4mm VFQFPN; minimal board

space

• Bypass mode additive phase jitter 160fs rms typ. @

156.25M (1.5M to 10M)

Block Diagram

Note: Resistors default to internal on xx42/xx52 devices. P2 devices have programmable default impedances on an output-by-output basis.

9DBL02 OCTOBER 6, 2016

12 3 4 5 6 7...19

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