Datasheet > 9DBL02

9DBL02

更新时间： 2022-02-26 11:00:07

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	300K
描述
2-output 3.3V PCIe Zero-Delay Buffer

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9DBL02 数据手册

9DBL02 DATASHEET

Pin Descriptions

Pin#

Pin Name

Pin Type

Description

True clock of differential feedback. The feedback output and

FB_DNC

DNC

feedback input are connected internally on this pin. Do not connect

anything to this pin.

Complement clock of differential feedback. The feedback output

and feedback input are connected internally on this pin. Do not

connect anything to this pin.

3.3V power for differential input clock (receiver). This VDD should

be treated as an Analog power rail and filtered appropriately.

True Input for differential reference clock.

Complementary Input for differential reference clock.

Ground pin for digital circuitry

Data pin for SMBus circuitry, 3.3V tolerant.

3.3V digital power (dirty power)

Clock pin of SMBus circuitry, 3.3V tolerant.

Power supply for outputs,nominal 3.3V.

No Connection.

FB_DNC#

VDDR3.3

DNC

PWR

CLK_IN

CLK_IN#

GNDDIG

SDATA_3.3

VDDDIG3.3

SCLK_3.3

GND

I/O

PWR

N/A

OUT

10 VDDO3.3

11 NC

12 NC

13 DIF0

14 DIF0#

No Connection.

Differential true clock output

Differential Complementary clock output

Active low input for enabling DIF pair 0. This pin has an internal pull-

down.

15 vOE0#

1 =disable outputs, 0 = enable outputs

3.3V power for the PLL core.

Differential true clock output

Differential Complementary clock output

Active low input for enabling DIF pair 1. This pin has an internal pull-

down.

16 VDDA3.3

17 DIF1

18 DIF1#

PWR

OUT

19 vOE1#

1 =disable outputs, 0 = enable outputs

No Connection.

20 NC

N/A

21 VDDO3.3

PWR

Power supply for outputs,nominal 3.3V.

Input notifies device to sample latched inputs and start up on first

high assertion. Low enters Power Down Mode, subsequent high

assertions exit Power Down Mode. This pin has internal pull-up

resistor.

22 ^CKPWRGD_PD#

23 vSADR_tri

LATCHED Tri-level latch to select SMBus Address. See SMBus Address

Selection Table.

Trilevel input to select High BW, Bypass or Low BW mode. This

pin is biased to VDD/2 (Bypass mode) with internal pull up/pull down

resistors. See PLL Operating Mode Table for Details.

connect epad to ground.

LATCHED

24 ^vHIBW_BYPM_LOBW#

25 epad

GND

NOTE: DNC indicates Do Not Connect anything to this pin.

OCTOBER 6, 2016

2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER

1 234 5 6 7...19

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