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9DBL0252 PDF预览

9DBL0252

更新时间: 2024-11-10 14:57:15
品牌 Logo 应用领域
瑞萨 - RENESAS PC
页数 文件大小 规格书
33页 1433K
描述
2-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer

9DBL0252 数据手册

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Datasheet  
9DBL02x2/9DBL04x2/9DBL06x1/9DBL08x1C  
2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers  
The 9DBL02x2/9DBL04x2/9DBL06x1/9DBL08x1C  
Features  
▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs  
buffers are low-power, high-performance members of  
Renesas' full featured PCIe family. The buffers  
support PCIe Gen1 through Gen5.  
eliminate 4 resistors per output pair  
▪ 9DBLxx4x devices provide integrated 100Ω  
terminations  
PCIe Clocking Architectures  
▪ Common Clocked (CC)  
▪ 9DBLxx5x devices provide integrated 85Ω  
terminations  
▪ Independent Reference (IR) with and without  
spread spectrum (SRIS, SRNS)  
▪ See AN-891 for easy coupling to other logic  
families  
▪ Spread-spectrum compatible  
Typical Applications  
▪ PCIe Riser Cards  
▪ nVME Storage  
▪ Dedicated OE# pin for each output  
▪ 1MHz to 200MHz operation in fan-out mode  
▪ 3 selectable SMBus addresses  
▪ Networking  
▪ Extensive SMBus-selectable features allow  
optimization to customer requirements  
▪ Accelerators  
▪ Industrial Control/Embedded  
▪ SMBus interface not required for device operation  
▪ -40°C to +85°C operating temperature range  
▪ Space-saving packages:  
Key Specifications  
▪ Additive PCIe Gen5 CC jitter < 60fs RMS (fanout  
mode)  
• 4 × 4 mm 24-VFQFPN (9DBL02x2C)  
• 5 × 5 mm 32-VFQFPN (9DBL04x2C)  
• 5 × 5 mm 40-VFQFPN (9DBL06x1C)  
• 6 × 6 mm 48-VFQFPN (9DBL08x1C)  
▪ PCIe Gen5 CC jitter < 150fs RMS (High-BW ZDB  
Mode)  
FB_DNC#  
FB_DNC#  
PLL  
CLK_IN#  
CLK_IN  
DIFn#  
DIFn  
2, 4, 6, 8  
Outputs  
n = 1, 3, 5, 7  
vSADR_tri  
SMBus  
Factory  
Configuration  
SCLK_3.3  
Engine  
SDATA_3.3  
DIF0#  
DIF0  
^vHIBW_BYPM-LOBW#  
^CKPWRGD_PD#  
vOE[n:0]#  
Control Logic  
n+1  
Figure 1. Block Diagram  
R31DS0116EU0102 Rev.1.02  
Nov 25, 2022  
Page 1  
© 2022 Renesas Electronics  

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