Datasheet > 9DBL0243

9DBL0243

更新时间： 2023-12-20 18:44:28

品牌	Logo	应用领域
瑞萨 - RENESAS		PC
页数	文件大小	规格书
32页	1355K
描述
2-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer with Loss of Signal Indicator

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数据手册

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9DBL0243 数据手册

9DBL02x3/9DBL04x3/

9DBL06x3/9DBL08x3

2 to 8-Output 3.3V PCIe

Zero-Delay/Fanout Buffers with LOS

Datasheet

Description

The 9DBL02x3/9DBL04x3/ 9DBL06x3/9DBL08x3 buffers are

low-power, high-performance members of Renesas' full featured

PCIe family. The buffers support PCIe Gen1–5 and provide a Loss

of Signal (LOS) indicator.

Features

▪ LOS open-drain output indicates loss of input clock

▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4

resistors per output pair

▪ 9DBLxx4x devices provide integrated 100Ω terminations

▪ 9DBLxx5x devices provide integrated 85Ω terminations

▪ See AN-891 for easy coupling to other logic families

▪ Spread-spectrum compatible

PCIe Clocking Architectures

▪ Common Clocked (CC)

▪ Independent Reference (IR) with/without SSC (SRIS, SRNS)

▪ Dedicated OE# pin for each output

▪ 1MHz to 200MHz operation in fan-out mode

▪ 3 selectable SMBus addresses

Typical Applications

▪ Extensive SMBus-selectable features allow optimization to

customer requirements

▪ PCIe Riser Cards

▪ nVME Storage

▪ SMBus interface not required for device operation

▪ -40°C to +85°C operating temperature range

▪ Networking

▪ Accelerators

▪ Space-saving 4 × 4 mm 24-VFQFPN to 6 × 6 mm 48-VFQFPN

packages (see Ordering Information table for details)

▪ Industrial Control/Embedded

Key Specifications

▪ Additive PCIe Gen5 CC jitter < 60fs RMS (fanout mode)

▪ PCIe Gen5 CC jitter < 150fs RMS (High-BW ZDB Mode)

Block Diagram

FB_DNC#

PLL

CLK_IN#

CLK_IN

DIFn#

DIFn

2, 4, 6, 8

Outputs

n = 1, 3, 5, 7

vSADR_tri

SCLK_3.3

SDATA_3.3

SMBus

Engine Configuration

Factory

DIF0#

DIF0

^vHIBW_BYPM-LOBW#

^CKPWRGD_PD#

vOE[n:0]#

Control Logic

n+1

LOS

Logic

December 9, 2022

12 3 4 5 6 7...32

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