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9DBL02 PDF预览

9DBL02

更新时间: 2022-02-26 11:00:07
品牌 Logo 应用领域
艾迪悌 - IDT PC
页数 文件大小 规格书
19页 300K
描述
2-output 3.3V PCIe Zero-Delay Buffer

9DBL02 数据手册

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9DBL02 DATASHEET  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the 9DBL02. These ratings, which are standard values  
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions  
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating  
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended  
operating temperature range.  
PARAMETER  
SYMBOL  
CONDITIONS  
UNITS NOTES  
MIN  
-0.5  
TYP  
MAX  
4.6  
VDD+0.5  
Supply Voltage  
Input Voltage  
VDDx  
VIN  
V
V
1,2  
1,3  
Input High Voltage, SMBus  
VIHSMB  
Ts  
Tj  
SMBus clock and data pins  
Human Body Model  
3.9  
150  
125  
V
1
1
1
1
Storage Temperature  
Junction Temperature  
Input ESD protection  
-65  
°C  
°C  
V
ESD prot  
2500  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
3 Not to exceed 4.6V.  
Electrical Characteristics–Clock Input Parameters  
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
900  
UNITS NOTES  
Input Crossover Voltage -  
DIF_IN  
VCROSS  
Cross Over Voltage  
150  
mV  
1
Input Swing - DIF_IN  
Input Slew Rate - DIF_IN  
Input Leakage Current  
VSWING  
dv/dt  
IIN  
Differential value  
Measured differentially  
300  
0.4  
-5  
mV  
V/ns  
uA  
1
1,2  
8
5
VIN = VDD , VIN = GND  
Input Duty Cycle  
dtin  
Measurement from differential wavefrom  
45  
0
55  
125  
%
1
1
Input Jitter - Cycle to Cycle  
JDIFIn  
Differential Measurement  
ps  
1 Guaranteed by design and characterization, not 100% tested in production.  
2Slew rate measured through +/-75mV window centered around differential zero  
Electrical Characteristics–SMBus Parameters  
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
SMBus Input Low Voltage  
SMBus Input High Voltage  
VILSMB  
VIHSMB  
VDDSMB = 3.3V  
VDDSMB = 3.3V  
@ IPULLUP  
0.8  
3.6  
0.4  
V
V
2.1  
SMBus Output Low Voltage VOLSMB  
V
SMBus Sink Current  
Nominal Bus Voltage  
SCLK/SDATA Rise Time  
IPULLUP  
VDDSMB  
tRSMB  
@ VOL  
4
mA  
V
2.7  
3.6  
1000  
300  
(Max VIL - 0.15) to (Min VIH + 0.15)  
(Min VIH + 0.15) to (Max VIL - 0.15)  
ns  
ns  
1
1
SCLK/SDATA Fall Time  
SMBus Operating  
Frequency  
tFSMB  
fSMB  
SMBus operating frequency  
500  
kHz  
2,3  
1 Guaranteed by design and characterization, not 100% tested in production.  
2. The device must be powered up for the SMBus to function.  
3.  
The differential input clock must be running for the SMBus to be active  
OCTOBER 6, 2016  
5
2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER  

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