Datasheet > 9DBL02

9DBL02

更新时间： 2022-02-26 11:00:07

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	300K
描述
2-output 3.3V PCIe Zero-Delay Buffer

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9DBL02 数据手册

9DBL02 DATASHEET

Test Loads

Terminations

Device

Low-Power Differential Output Test Load

Zo (Ω)

100

Rs (Ω)

None needed

7.5

Prog.

N/A

None needed

Prog.

9DBL0242

9DBL0252

9DBL02P2

9DBL0242

9DBL0252

9DBL02P2

5 inches

Zo=100ohm

2pF

Note: The device can drive transmission line lengths greater

than those specified by the PCIe SIG

Alternate Terminations

The 9DBL family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with

IDT's "Universal" Low-Power HCSL Outputs” for details.

2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER

OCTOBER 6, 2016

1 2 345 6 7...19

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型号	品牌	描述	获取价格	数据表
9DBL0242	IDT	2-output 3.3V PCIe Zero-Delay Buffer	获取价格
9DBL0242	RENESAS	2-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer	获取价格
9DBL0242BKILF	IDT	2-output 3.3V PCIe Zero-Delay Buffer	获取价格
9DBL0242BKILFT	IDT	2-output 3.3V PCIe Zero-Delay Buffer	获取价格
9DBL0243	IDT	2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator	获取价格
9DBL0243	RENESAS	2-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer with Loss of Signal Indicator	获取价格