Datasheet > 9DBL0243

9DBL0243

更新时间： 2022-02-26 11:13:26

品牌	Logo	应用领域
艾迪悌 - IDT		瞄准线
页数	文件大小	规格书
22页	387K
描述
2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator

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9DBL0243 数据手册

9DBL0243 / 9DBL0253

2-Output 3.3V LP-HCSL Zero-Delay

Buffer with LOS Indicator

Datasheet

Description

Features

▪ LOS indicator signals loss of input clock; adds fault tolerance,

The 9DBL0243 / 9DBL0253 devices are 3.3V members of IDT's

Full-Featured PCIe clock family. They support PCIe Gen1–4

Common Clock (CC) architectures and also support NVLINK

applications. The 9DBL0243 / 9DBL0253 parts have a Loss of

Signal (LOS) indicator to support fault-tolerant, high-reliability

systems.

eases system diagnostics

▪ Direct connection to 100Ω (0243) or 85Ω (0253) transmission

lines; saves 8 resistors compared to standard PCIe devices

▪ 100mW typical power consumption in PLL mode; eliminates

thermal concerns

▪ OE# pin for each DIF output; supports DIF power management

Typical Applications

▪ HCSL-compatible differential input; can be driven by common

▪ PCIe Gen1–4 and NVLINK clock distribution for Riser Cards

clock sources

▪ Storage and Networking

▪ JBOD

▪ Spread spectrum tolerant; allows reduction of EMI

▪ Outputs blocked until PLL is locked; clean system start-up

▪ Communications

▪ Access Points

▪ Pin/SMBus selectable PLL bandwidth and PLL Bypass;

minimize phase jitter for each application

▪ 3 selectable SMBus addresses; multiple devices can easily

Output Features

share an SMBus segment

▪ Loss Of Signal (LOS) open drain output

▪ 2 1–200 MHz Low-Power (LP) HCSL DIF pairs

— 9DBL0243 default Zout = 100Ω

▪ SMBus-selectable features allows optimization to customer

requirements:

— control input polarity

— 9DBL0253 default Zout = 85Ω

— control input pull-up/downs

— slew rate for each output

— differential output amplitude

— output impedance for each output

▪ Easy AC-coupling to other logic families; see IDT application

note AN-891.

Key Specifications

▪ PCIe Gen1–4 CC compliant in ZDB or fanout buffer mode

▪ Supports NVLINK at 156.25MHz in ZDB or fanout buffer mode

▪ DIF cycle-to-cycle jitter < 50ps

▪ Contact IDT for quick-turn customization of SMBus defaults;

allows exact optimization to customer requirements.

▪ 4 × 4 mm 24-VFQFPN; minimal board space

▪ DIF output-to-output skew < 50ps

▪ Bypass Mode additive phase jitter is 0ps typical rms for PCIe

▪ Bypass Mode additive phase jitter 160fs rms typical at 156.25M

(1.5MHz to 10MHz)

Block Diagram

vOE(1:0)#

DIF1

Spread

Spectrum

Compatible PLL

CLK_IN

DIF0

CLK_IN#

vSADR_tri

^vHIBW_BYPM_LOBW#

Control

Logic

^CKPWRGD_PD#

SDATA_3.3

LOS

Logic

LOS

SCLK_3.3

March 15, 2017

12 3 4 5 6 7...22

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与9DBL0243相关器件

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9DBL0243ANLGI	IDT	2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator	获取价格
9DBL0243ANLGI8	IDT	2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator	获取价格
9DBL0252	IDT	2-output 3.3V PCIe Zero-Delay Buffer	获取价格
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