Datasheet > 9DBL0455

9DBL0455

更新时间： 2023-12-20 18:45:09

品牌	Logo	应用领域
瑞萨 - RENESAS		PC 瞄准线
页数	文件大小	规格书
16页	783K
描述
4-Output 3.3V PCIe Gen1–5 Clock Fanout Buffer with LOS

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9DBL0455 数据手册

2 and 4-Output 3.3V PCIe Gen1–5

Clock Fanout Buffers with LOS

9DBL0255/9DBL0455

Datasheet

Description

Features

▪ FPS: VDD may be applied with floating input clock, or input

clock may be driven before VDD is applied

The 9DBL0255/9DBL0455 are 2 and 4-output PCIe Clock fan-out

buffers for PCIe Gen1–5 applications. Both parts have an open

drain Loss of Signal (LOS) output to indicate the absence or

presence of an input clock. The LOS circuit also implements

Automatic Clock Parking (ACP) to cleanly park the outputs

low/low when the input clock goes away. The devices implement

several additional features to aid robust designs. Flexible Power

Sequencing (FPS) ensures well-defined behavior under various

power up scenarios, while Power Down Tolerant (PDT) ESD

protection allows input pins to be driven before VDD is applied.

The 9DBL0255/9DBL0455 are spread-spectrum compatible and

provide direct connection to 85Ω transmission lines. They can also

be used in 100Ω environments with simple external series

resistors.

▪ ACP: Outputs automatically park low/low when LOS occurs

and cleanly start when LOS is removed

▪ PDT: Input pins may be driven before VDD is applied and will

not damage the device

▪ 2 or 4 Low-power HCSL (LP-HCSL) DIF pairs

▪ 85Ω loads require 0 termination resistors

▪ 100Ω loads require only 2 series resistors per output

▪ OE# pin for each output

▪ Spread-spectrum tolerant

▪ Industrial temperature range (-40°C to +85°C)

▪ Space saving 3 × 3 mm 16-VFQFPN (9DBL0255)

▪ Space saving 4 × 4 mm 20-VFQFPN (9DBL0455)

PCIe Architectures

▪ Common Clocked (CC)

▪ Independent Reference Clock (SRIS, SRnS)

▪ Easy AC-coupling to other logic families. See application note

AN-891.

Key Specifications

Typical Applications

▪ Input-to-output delay < 3ns

▪ PCIe clock distribution in:

▪ Output-to-output skew < 50ps

• PCIe Riser Cards

• NVME eSSD and JBOD

• High-Performance Computing and Accelerators

▪ Operating frequency up to 267MHz (9DBL0455)

▪ Additive phase jitter < 15fs RMS for PCIe Gen5

▪ Additive phase jitter 46fs RMS (typical) at 156.25MHz

(12kHz–20MHz)

Block Diagram

DIF0#

DIF0

0.5V

50K

DIF1#

DIF1

CLK_IN

CLK_IN#

DIF2#

DIF2

50K

9DBL0455

only

DIF3#

9DBL0455

DIF3

vOE[3:2]#

only

LOS and OE

vOE[1:0]#

Logic

9DBL0255

only

LOS#

vTEST_EN

February 3, 2023

12 3 4 5 6 7...16

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