Datasheet > 9DBL02

9DBL02

更新时间： 2022-02-26 11:00:07

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	300K
描述
2-output 3.3V PCIe Zero-Delay Buffer

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数据手册

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9DBL02 数据手册

9DBL02 DATASHEET

Electrical Characteristics–DIF Low-Power HCSL Outputs

TA = T_AMB,Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

Slew rate

SYMBOL

CONDITIONS

MIN

TYP MAX UNITS NOTES

V/ns

dV/dt

Scope averaging on, fast setting

Scope averaging on, slow setting

Slew rate matching

1.2

2.8

1.9

3.1

1,2,3

1,2,4

Slew rate matching

Voltage High

dV/dt

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope

averaging on)

V_HIGH

660

768

-11

850

Voltage Low

V_LOW

-150

150

Max Voltage

Min Voltage

Crossing Voltage (abs)

Crossing Voltage (var)

Vmax

Vmin

Vcross_abs

Measurement on single ended signal using

absolute value. (Scope averaging off)

Scope averaging off

811

-49

357

1150

1,5

1,6

-300

250

550

140

-Vcross

Scope averaging off

¹Guaranteed by design and characterization, not 100% tested in production.

²Measured from differential waveform

³Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around

differential 0V.

⁴Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on

the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations.

⁵Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising

edge (i.e. Clock rising and Clock# falling).

⁶The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross

absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.

⁷At default SMBus settings.

Electrical Characteristics–Current Consumption

TA = T_AMB,Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

I_DDA

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

VDDA, PLL Mode @100MHz

VDDDIG, PLL Mode @100MHz

Operating Supply Current

I_DDDIG

3.4

I_DDO+R

VDDO+VDDR, PLL Mode, All outputs @100MHz

VDDA, CKPWRGD_PD# = 0

0.6

3.0

0.9

1.0

4.3

1.3

I_DDRPD

I_DDDIGPD

I_DDAOPD

Powerdown Current

VDDDIG, CKPWRGD_PD# = 0

VDDO+VDDR, CKPWRGD_PD# = 0

¹Input clock stopped.

OCTOBER 6, 2016

2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER

1...4 5 678 9 10...19

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