9DBL02 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
-3dB point in High BW Mode (100MHz)
-3dB point in Low BW Mode (100MHz)
Peak Pass band Gain (100MHz)
2
1
3.3
1.5
0.8
4
2
2
MHz
MHz
dB
1,5
1,5
1
PLL Bandwidth
BW
PLL Jitter Peaking
Duty Cycle
tJPEAK
tDC
Measured differentially, PLL Mode
Measured differentially, Bypass Mode
Bypass Mode, VT = 50%
45
-1
50
0.0
3406
8
55
1
%
%
1
Duty Cycle Distortion
tDCD
1,3
1
tpdBYP
tpdPLL
tsk3
2500
-100
4500
100
ps
ps
Skew, Input to Output
PLL Mode VT = 50%
1,4
Skew, Output to Output
Jitter, Cycle to cycle
VT = 50%
PLL mode
Additive Jitter in Bypass Mode
21
15
0.1
55
50
1
ps
ps
ps
1,4
1,2
1,2
tjcyc-cyc
1 Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4 All outputs at default slew rate
5 The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common Clocked
(CC) Architectures
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
INDUSTRY
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
23
MAX
32
UNITS Notes
ps (p-p) 1,2,3,5
LIMIT
86
tjphPCIeG1-CC
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
ps
0.6
1.7
0.8
3
1,2,5
(rms)
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
PCIe Gen 4
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
tjphPCIeG2-CC
Phase Jitter,
PLL Mode
ps
2.1
3.1
1,2,5
(rms)
ps
0.48
0.48
0.01
1
tjphPCIeG3-CC
tjphPCIeG4-CC
tjphPCIeG1-CC
0.4
0.4
0.0
1,2,5
(rms)
ps
(rms)
0.5
1,2,5
ps
PCIe Gen 1
1,2,5
(p-p)
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
PCIe Gen 4
ps
0.0
0.0
0.01
0.01
1,2,4,5
(rms)
tjphPCIeG2-CC
Additive Phase Jitter,
n/a
ps
Bypass mode
1,2,4,5
(rms)
ps
tjphPCIeG3-CC
0.0
0.0
0.01
0.01
1,2,4,5
(rms)
ps
tjphPCIeG4-CC
1,2,4,5
(rms)
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
1 Applies to all outputs.
2 Based on PCIe Base Specification Rev4.0 version 0.7draft. See http://www.pcisig.com for latest specifications.
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 For RMS values additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2] where a is rms input jitter and c is rms total jitter.
5 Driven by 9FGL0841 or equivalent
2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
8
OCTOBER 6, 2016
5秒后页面跳转
SG3525资料手册详解：SG3525参数分析、引脚说明、应用介绍
AT89C51单片机资料手册详细解析及应用示例
CP2102资料手册解读：CP2102引脚说明、关键参数分析
资料手册解读：UC3842参数和管脚说明
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
