Datasheet > 9DBL02

9DBL02

更新时间： 2022-02-26 11:00:07

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	300K
描述
2-output 3.3V PCIe Zero-Delay Buffer

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9DBL02 数据手册

9DBL02 DATASHEET

Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Separate

Reference Independent Spread (SRIS) Architectures⁵

T_AMB= over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

INDUSTRY

LIMIT

PARAMETER

SYMBOL

t_jphPCIeG2-

CONDITIONS

MIN

TYP

1.2

MAX

1.5

UNITS Notes

PCIe Gen 2

(PLL BW of 16MHz , CDR = 5MHz)

1,2,5

(rms)

SRIS

Phase Jitter, PLL Mode

t_jphPCIeG3-

PCIe Gen 3

0.7

n/a

0.0

1,2,5,6

(rms)

(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)

SRIS

t_jphPCIeG2-

PCIe Gen 2

(PLL BW of 16MHz , CDR = 5MHz)

0.01

1,2,4,5

(rms)

Additive Phase Jitter,

Bypass mode

SRIS

n/a

t_jphPCIeG3-

PCIe Gen 3

0.01

1,2,4,5

(rms)

(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)

SRIS

¹Guaranteed by design and characterization, not 100% tested in production.

²Based on PCIe Base Specification Rev3.1a. These filters are different than Common Clock filters. See http://www.pcisig.com for latest specifications.

³Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

⁴For RMS values, additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2] where a is rms input jitter and c is rms total jitter.

⁵As of PCIe Base Specification Rev4.0 draft 0.7, SRIS is defined as "implementation dependent", with no firm specifcations.

⁶Certain customers have suggested a 0.7ps spec limit for Gen3 SRIS The device supports PCIe Gen3 SRIS in bypass mode.

Electrical Characteristics–Unfiltered Phase Jitter Parameters

TA = T_AMB,Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

INDUSTRY

PARAMETER

SYMBOL

t_jph156M

CONDITIONS

MIN

TYP

159

MAX

LIMIT

N/A

UNITS Notes

156.25MHz, 1.5MHz to 10MHz, -20dB/decade

rollover < 1.5MHz, -40db/decade rolloff > 10MHz

1,2,3

(rms)

Additive Phase Jitter,

Fanout Mode

t_jph156M12k-

156.25MHz, 12kHz to 20MHz, -20dB/decade

rollover <12kHz, -40db/decade rolloff > 20MHz

363

N/A

1,2,3

(rms)

¹Guaranteed by design and characterization, not 100% tested in production.

DRiven by Rohde&Schartz SMA100

³For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]

OCTOBER 6, 2016

2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER

1...6 7 8910 11 12...19

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