Datasheet > 9DBL02

9DBL02

更新时间： 2022-02-26 11:00:07

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	300K
描述
2-output 3.3V PCIe Zero-Delay Buffer

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9DBL02 数据手册

9DBL02 DATASHEET

Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating

Conditions

TA = T_AMB,Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

VDDx

CONDITIONS

Supply voltage for core and analog

Industrial range

MIN

3.135

-40

TYP

3.3

MAX

3.465

UNITS NOTES

Supply Voltage

Ambient Operating

Temperature

T_AMB

°C

Input High Voltage

V_IH

0.75 V_DDx

V_DDx+ 0.3

Single-ended inputs, except SMBus

Input Low Voltage

Input High Voltage

Input Mid Voltage

Input Low Voltage

V_IL

V_IHtri

V_IMtri

V_ILtri

I_IN

-0.3

0.25 V_DDx

V_DD+ 0.3

0.75 V_DDx

Single-ended tri-level inputs ('_tri' suffix)

0.4 V_DDx0.5 V_DDx0.6 V_DDx

-0.3

-5

0.25 V_DDx

Single-ended inputs, V_IN= GND, V_IN= VDD

Single-ended inputs

_IN= 0 V; Inputs with internal pull-up resistors

_IN= VDD; Inputs with internal pull-down resistors

Bypass mode

Input Current

I_INP

-50

200

140

175

MHz

100MHz PLL mode

100.00

50.00

Input Frequency

F_IN

50MHz PLL mode

125MHz PLL mode

125.00

Pin Inductance

Capacitance

L_pin

C_IN

Logic Inputs, except DIF_IN

DIF_IN differential clock inputs

Output pin capacitance

1.5

C_{INDIF_IN}

C_OUT

2.7

From V_DDPower-Up and after input clock

stabilization or de-assertion of PD# to 1st clock

Clk Stabilization

T_STAB

1,2

Input SS Modulation

Frequency PCIe

Allowable Frequency for PCIe Applications

(Triangular Modulation)

f_MODINPCIe

kHz

Input SS Modulation

Frequency non-PCIe

Allowable Frequency for non-PCIe Applications

(Triangular Modulation)

f_MODIN

t_LATOE#

t_DRVPD

kHz

clocks

DIF start after OE# assertion

DIF stop after OE# deassertion

DIF output enable after

OE# Latency

Tdrive_PD#

1,3

300

PD# de-assertion

Tfall

t_F

Fall time of single-ended control inputs

Trise

t_R

Rise time of single-ended control inputs

¹Guaranteed by design and characterization, not 100% tested in production.

²Control input must be monotonic from 20% to 80% of input swing.

³Time from deassertion until outputs are >200 mV

2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER

OCTOBER 6, 2016

1...3 4 567 8 9...19

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