Datasheet > 9DBL02

9DBL02

更新时间： 2022-02-26 11:00:07

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	300K
描述
2-output 3.3V PCIe Zero-Delay Buffer

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数据手册

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9DBL02 数据手册

9DBL02 DATASHEET

Pin Configuration

24 23 22 21 20 19

FB_DNC 1

FB_DNC# 2

VDDR3.3 3

CLK_IN 4

DIF1#

DIF1

9DBL0242/52/P2

connect epad to

GND

VDDA3.3

vOE0#

DIF0#

CLK_IN# 5

GNDDIG 6

13 DIF0

9 10 11 12

24-pin VFQFPN, 4x4 mm, 0.5mm pitch

^ prefix indicates internal 120KOhm pull up resistor

^v prefix indicates internal 120KOhm pull up AND

pull down resistor (biased to VDD/2)

v prefix indicates internal 120KOhm pull down

resistor

SMBus Address Selection Table

Read/Write bit

SADR

Address

1101011

1101100

1101101

State of SADR on first application of

CKPWRGD_PD#

Note: If not using CKPWRGD (CKPWRGD tied to VDD3.3), all 3.3V VDD need to transition

from 2.1V to 3.135V in <300usec.

Power Management Table

SMBus

OE bit

DIFx/DIFx#

CKPWRGD_PD#

CLK_IN

OEx# Pin

PLL

True O/P

Low¹

Comp. O/P

Low¹

Off

On³

Running

Disabled¹

Running

Disabled¹

1. The output state is set by B11[1:0] (Low/Low default)

2. Input polarities defined as default values for xx41/xx51 devices.

3. If Bypass mode is selected, the PLL will be off, and outputs will be running.

Power Connections

PLL Operating Mode

Pin Number

Description

Byte1 [7:6] Byte1 [4:3]

VDD

GND

HiBW_BypM_LoBW#

MODE

PLL Lo BW

Bypass

Readback

Control

Input receiver analog

Digital Power

DIF outputs

10,21

PLL Hi BW

PLL Analog

2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER

OCTOBER 6, 2016

123 4 5 6 7...19

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与9DBL02相关器件

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9DBL0242	IDT	2-output 3.3V PCIe Zero-Delay Buffer	获取价格
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9DBL0242BKILF	IDT	2-output 3.3V PCIe Zero-Delay Buffer	获取价格
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9DBL0243	IDT	2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator	获取价格
9DBL0243	RENESAS	2-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer with Loss of Signal Indicator	获取价格