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935305331147

更新时间： 2024-09-17 19:45:39
品牌 Logo 应用领域
恩智浦 - NXP 外围集成电路
页数 文件大小 规格书
70页 2486K
描述
Parallel I/O Port

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935305331147 技术参数

生命周期：Active包装说明：,
Reach Compliance Code：unknown风险等级：5.75
uPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches：1

935305331147 数据手册

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PCAL6524  
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O  
expander with Agile I/O features, interrupt output and reset  
Rev. 2 — 15 May 2019  
Product data sheet  
1. General description  
The PCAL6524 is a 24-bit general purpose I/O expander that provides remote I/O  
expansion for most microcontroller families via the Fast-mode Plus (Fm+) I2C-bus  
interface. The ultra low-voltage interface allows for direct connection to a microcontroller  
operating down to 0.8 V.  
NXP I/O expanders provide a simple solution when additional I/Os are needed while  
keeping interconnections to a minimum, for example, in battery-powered mobile  
applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing  
a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage  
level down to 0.8 V to I/O devices operating at a different voltage level 1.65 V to 5.5 V.  
The PCAL6524 has built-in level shifting feature that makes these devices extremely  
flexible in mixed power supply systems where communication between incompatible I/O  
voltages is required, allowing seamless communications with next-generation low voltage  
microprocessors and microcontrollers on the interface side (SDA/SCL) and peripherals at  
a higher voltage on the port side.  
There are two supply voltages for PCAL6524: VDD(I2C-bus) and VDD(P). VDD(I2C-bus) provides  
the supply voltage for the interface at the master side (for example, a microcontroller) and  
the VDD(P) provides the supply for core circuits and Port P. The bidirectional voltage level  
translation in the PCAL6524 is provided through VDD(I2C-bus). VDD(I2C-bus) should be  
connected to the VDD of the external SCL/SDA lines. This indicates the VDD level of the  
I2C-bus to the PCAL6524, while the voltage level on Port P of the PCAL6524 is  
determined by the VDD(P)  
.
The PCAL6524 fully meets the Fm+ I2C-bus specification at speeds to 1 MHz and  
implements Agile I/O, which are additional features specifically designed to enhance the  
I/O. These additional features are: programmable output drive strength, latchable inputs,  
programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register,  
programmable open-drain or push-pull outputs.  
Additional Agile I/O Plus features include I2C software reset and device ID. Interrupts can  
be specified by level or edge, and can be cleared individually without disturbing the other  
interrupt events. Also, switch debounce hardware is implemented.  
At power-on, the I/Os are configured as inputs. However, the system master can enable  
the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for  
each input or output is kept in the corresponding input or output register. The polarity of  
the Input Port register can be inverted with the Polarity Inversion register, saving external  
logic gates. Programmable pull-up and pull-down resistors eliminate the need for discrete  
components.  
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