Datasheet > 935307226518

935307226518

更新时间： 2024-09-18 09:27:43

品牌	Logo	应用领域
恩智浦 - NXP		商用集成电路
页数	文件大小	规格书
32页	412K
描述
IC DISPLAYPORT TO LVDS 56HVQFN

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技术参数
数据手册

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935307226518 技术参数

是否无铅：	不含铅	生命周期：	Active
包装说明：	,	Reach Compliance Code：	unknown
风险等级：	5.7	商用集成电路类型：	CONSUMER CIRCUIT
Base Number Matches：	1

935307226518 数据手册

PTN3460

eDP to LVDS bridge IC

Rev. 4 — 12 March 2014

Product data sheet

1. General description

PTN3460 is an (embedded) DisplayPort to LVDS bridge device that enables connectivity

between an (embedded) DisplayPort (eDP) source and LVDS display panel. It processes

the incoming DisplayPort (DP) stream, performs DP to LVDS protocol conversion and

transmits processed stream in LVDS format.

PTN3460 has two high-speed ports: Receive port facing DP Source (for example,

CPU/GPU/chip set), Transmit port facing the LVDS receiver (for example., LVDS display

panel controller). The PTN3460 can receive DP stream at link rate 1.62 Gbit/s or

2.7 Gbit/s and it can support 1-lane or 2-lane DP operation. It interacts with DP source via

DP Auxiliary (AUX) channel transactions for DP link training and setup.

It supports single bus or dual bus LVDS signaling with color depths of 18 bits per pixel or

24 bits per pixel and pixel clock frequency up to 112 MHz. The LVDS data packing can be

done either in VESA or JEIDA format. Also, the DP AUX interface transports

I²C-over-AUX commands and support EDID-DDC communication with LVDS panel. To

support panels without EDID ROM, the PTN3460 can emulate EDID ROM behavior

avoiding specific changes in system video BIOS.

PTN3460 provides high flexibility to optimally fit under different platform environments. It

supports three configuration options: multi-level configuration pins, DP AUX interface, and

I²C-bus interface.

PTN3460 can be powered by either 3.3 V supply only or dual supplies (3.3 V/1.8 V) and is

available in the HVQFN56 7 mm  7 mm package with 0.4 mm pitch.

2. Features and benefits

2.1 Device features

 Embedded microcontroller and on-chip Non-Volatile Memory (NVM) allow for flexibility

in firmware updates

 LVDS panel power-up (/down) sequencing control

 Firmware controlled panel power-up (/down) sequence timing parameters

 No external timing reference needed

 EDID ROM emulation to support panels with no EDID ROM

 Supports EDID structure v1.3

 On-chip EDID emulation up to seven different EDID data structures

 eDP complying PWM signal generation or PWM signal pass through from eDP source

12 3 4 5 6 7...32

中文翻译

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