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74VHC126MTR PDF预览

74VHC126MTR

更新时间: 2024-11-24 04:48:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
12页 243K
描述
QUAD BUS BUFFERS (3-STATE)

74VHC126MTR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.1
控制类型:ENABLE HIGH系列:AHC/VHC
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A湿度敏感等级:1
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/5.5 V
Prop。Delay @ Nom-Sup:8.5 ns传播延迟(tpd):13 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

74VHC126MTR 数据手册

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74VHC126  
QUAD BUS BUFFERS (3-STATE)  
HIGH SPEED: t = 3.8ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4 µA (MAX.) at T =25°C  
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
POWER DOWN PROTECTION ON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
SOP  
TSSOP  
|I | = I = 8 mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
Table 1: Order Codes  
PACKAGE  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
T & R  
V
CC  
SOP  
74VHC126MTR  
74VHC126TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 126  
TSSOP  
IMPROVED LATCH-UP IMMUNITY  
LOW NOISE: V  
= 0.8V (MAX.)  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface 5V to 3V.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
OLP  
DESCRIPTION  
The 74VHC126 is an advanced high-speed  
CMOS QUAD BUS BUFFERs fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS technology.  
The device requires the 3-STATE control input G  
to be set low to place the output go in to the high  
impedance state.  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 5  
1/12  
November 2004  

74VHC126MTR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHC126DR TI

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