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74VHC132MX_NL PDF预览

74VHC132MX_NL

更新时间: 2024-11-02 04:48:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 239K
描述
Quad 2-Input NAND Schmitt Trigger

74VHC132MX_NL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.150 INCH, LEAD FREE, MS-012, SOIC-14
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.17
Is Samacsys:N系列:AHC/VHC
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:8.6235 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.008 A
湿度敏感等级:1功能数量:4
输入次数:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP36,.4,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/5.5 V
Prop。Delay @ Nom-Sup:11 ns传播延迟(tpd):17.5 ns
认证状态:Not Qualified施密特触发器:YES
座面最大高度:1.753 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

74VHC132MX_NL 数据手册

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74VHC132  
QUAD 2-INPUT SCHMITT NAND GATE  
HIGH SPEED: t = 3.9 ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 2 µA (MAX.) at T =25°C  
CC  
A
TYPICAL HYSTERESIS:  
V = 1V at V = 4.5V  
h
CC  
POWER DOWN PROTECTION ON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
SOP  
TSSOP  
|I | = I = 8 mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
Table 1: Order Codes  
PACKAGE  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
V
T & R  
CC  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 132  
IMPROVED LATCH-UP IMMUNITY  
SOP  
74VHC132MTR  
74VHC132TTR  
TSSOP  
LOW NOISE: V  
= 0.8V (MAX.)  
OLP  
Pin configuration and function are the same as  
those of the 74VHC00 but the 74VHC132 has  
hysteresis.  
This together with its schmitt trigger function  
allows it to be used on line receivers with slow  
rise/fall input signals.  
DESCRIPTION  
The 74VHC132 is an advanced high-speed  
CMOS QUAD 2-INPUT SCHMITT NAND GATE  
fabricated with sub-micron silicon gate and  
2
double-layer metal wiring C MOS technology.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface 5V to 3V.  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 4  
1/11  
November 2004  

74VHC132MX_NL 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHC00NSR TI

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