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74VHC132 PDF预览

74VHC132

更新时间: 2024-01-03 14:24:56
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件
页数 文件大小 规格书
7页 56K
描述
QUAD 2-INPUT SCHMITT NAND GATE

74VHC132 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-14针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:16 weeks风险等级:5.22
Is Samacsys:N系列:AHC/VHC
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.008 A
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/5.5 VProp。Delay @ Nom-Sup:11 ns
传播延迟(tpd):17.5 ns认证状态:Not Qualified
施密特触发器:YES座面最大高度:1.2 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

74VHC132 数据手册

 浏览型号74VHC132的Datasheet PDF文件第2页浏览型号74VHC132的Datasheet PDF文件第3页浏览型号74VHC132的Datasheet PDF文件第4页浏览型号74VHC132的Datasheet PDF文件第5页浏览型号74VHC132的Datasheet PDF文件第6页浏览型号74VHC132的Datasheet PDF文件第7页 
74VHC132  
QUAD 2-INPUT SCHMITT NAND GATE  
PRELIMINARY DATA  
HIGH SPEED:tPD =4.9ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
ICC =2 µA (MAX.) at TA =25 oC  
TYPICAL HYSTERESIS:Vh = 1V atVCC = 4.5V  
POWERDOWN PROTECTIONON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
M
T
(Micro Package)  
(TSSOPPackage)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
OPERATING VOLTAGERANGE:  
ORDER CODES :  
74VHC132M  
74VHC132T  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
Pin configuration and function are the same as  
those of the VHC00 but the VHC132 has  
hysteresis.  
VCC (OPR)= 2V to 5.5V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES132  
IMPROVED LATCH-UP IMMUNITY  
LOWNOISE:VOLP = 0.8V(Max.)  
This together with its schmitt trigger function  
allows it to be used on line receivers with slow  
rise/fall input signals.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74VHC132 is an advanced high-speed  
CMOS QUAD 2-INPUT SCHMITT NAND GATE  
fabricated with sub-micron silicon gate and  
double-layermetal wiring C2MOS technology.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/7  
June 1999  

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