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74VHC132TTR PDF预览

74VHC132TTR

更新时间: 2024-11-02 04:48:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
11页 239K
描述
QUAD 2-INPUT SCHMITT NAND GATE

74VHC132TTR 数据手册

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74VHC132  
QUAD 2-INPUT SCHMITT NAND GATE  
HIGH SPEED: t = 3.9 ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 2 µA (MAX.) at T =25°C  
CC  
A
TYPICAL HYSTERESIS:  
V = 1V at V = 4.5V  
h
CC  
POWER DOWN PROTECTION ON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
SOP  
TSSOP  
|I | = I = 8 mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
Table 1: Order Codes  
PACKAGE  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
V
T & R  
CC  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 132  
IMPROVED LATCH-UP IMMUNITY  
SOP  
74VHC132MTR  
74VHC132TTR  
TSSOP  
LOW NOISE: V  
= 0.8V (MAX.)  
OLP  
Pin configuration and function are the same as  
those of the 74VHC00 but the 74VHC132 has  
hysteresis.  
This together with its schmitt trigger function  
allows it to be used on line receivers with slow  
rise/fall input signals.  
DESCRIPTION  
The 74VHC132 is an advanced high-speed  
CMOS QUAD 2-INPUT SCHMITT NAND GATE  
fabricated with sub-micron silicon gate and  
2
double-layer metal wiring C MOS technology.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface 5V to 3V.  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 4  
1/11  
November 2004  

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