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74VHC08M PDF预览

74VHC08M

更新时间: 2024-11-03 22:56:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器逻辑集成电路光电二极管输入元件PC
页数 文件大小 规格书
7页 56K
描述
QUAD 2-INPUT AND GATE

74VHC08M 数据手册

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74VHC08  
QUAD 2-INPUT AND GATE  
PRELIMINARY DATA  
HIGH SPEED:tPD =4.3ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
I
CC =2 µA (MAX.) at TA =25 oC  
HIGH NOISEIMMUNITY:  
NIH = VNIL =28% VCC (MIN.)  
V
M
T
POWERDOWN PROTECTIONON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 5.5V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES08  
(Micro Package)  
(TSSOPPackage)  
ORDER CODES :  
74VHC08M  
74VHC08T  
The internal circuit is composed of 2 stages  
including buffer output, which provide high noise  
immunity and stable output.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
IMPROVED LATCH-UP IMMUNITY  
LOWNOISE:VOLP = 0.8V(Max.)  
DESCRIPTION  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
The 74VHC08 is an advanced high-speed CMOS  
QUAD 2-INPUT AND GATE fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/7  
June 1999  

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