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74VHC08MTCX_NL PDF预览

74VHC08MTCX_NL

更新时间: 2024-11-15 21:54:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
7页 101K
描述
Quad 2-Input AND Gate

74VHC08MTCX_NL 数据手册

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November 1992  
Revised February 2005  
74VHC08  
Quad 2-Input AND Gate  
General Description  
Features  
The VHC08 is an advanced high speed CMOS 2 Input  
AND Gate fabricated with silicon gate CMOS technology. It  
achieves the high-speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining the CMOS low  
power dissipation.  
High Speed: tPD 4.3 ns (typ) at TA 25 C  
High noise immunity: VNIH VNIL 28% VCC (min)  
Power down protection is provided on all inputs  
Low power dissipation: ICC  
2 A (Max) @ TA 25 C  
The internal circuit is composed of 4 stages including buffer  
output, which provide high noise immunity and stable out-  
put. An input protection circuit insures that 0V to 7V can be  
applied to the input pins without regard to the supply volt-  
age. This device can be used to interface 5V to 3V systems  
and two supply systems such as battery backup. This cir-  
cuit prevents device destruction due to mismatched supply  
and input voltages.  
Low noise: VOLP 0.8V (max)  
Pin and function compatible with 74HC08  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74VHC08M  
M14A  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
74VHC08MX_NL  
(Note 1)  
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
74VHC08SJ  
M14D  
MTC14  
MTC14  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74VHC08MTC  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74VHC08MTCX_NL  
(Note 1)  
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
74VHC08N  
N14A  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Truth Table  
A
L
B
L
O
L
Pin Descriptions  
Pin Names  
Description  
Inputs  
Outputs  
L
H
L
L
An, Bn  
On  
H
H
L
H
H
© 2005 Fairchild Semiconductor Corporation  
DS011514  
www.fairchildsemi.com  

74VHC08MTCX_NL 替代型号

型号 品牌 替代类型 描述 数据表
74VHC08MTC FAIRCHILD

完全替代

Quad 2-Input AND Gate
74VHC08MTCX ONSEMI

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四路 2 输入 AND 门极

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