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74V1G125_04 PDF预览

74V1G125_04

更新时间: 2024-11-06 04:01:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
10页 130K
描述
SINGLE BUS BUFFER (3-STATE)

74V1G125_04 数据手册

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74V1G125  
SINGLE BUS BUFFER (3-STATE)  
HIGH SPEED: t = 3.8ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 1µA (MAX.) at T =25°C  
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
POWER DOWN PROTECTION ON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
SOT23-5L  
SOT323-5L  
T & R  
|I | = I = 8mA (MIN) at V = 4.5V  
OH  
OL  
CC  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
PACKAGE  
V
CC  
SOT23-5L  
74V1G125STR  
74V1G125CTR  
IMPROVED LATCH-UP IMMUNITY  
SOT323-5L  
DESCRIPTION  
The 74V1G125 is an advanced high-speed CMOS  
SINGLE BUS BUFFER fabricated with sub-micron  
silicon gate and double-layer metal wiring C MOS  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface 5V to 3V.  
2
technology.  
3-STATE control input G has to be set HIGH to  
place the output into the high impedance state.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2004  
1/10  

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