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74V1G126C PDF预览

74V1G126C

更新时间: 2024-11-05 22:22:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 59K
描述
SINGLE BUS BUFFER 3-STATE

74V1G126C 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SC-70, 5 PIN
针数:5Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.88
Is Samacsys:N控制类型:ENABLE HIGH
系列:74VJESD-30 代码:R-PDSO-G5
JESD-609代码:e0长度:2 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.004 A位数:1
功能数量:1端口数量:2
端子数量:5最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP5/6,.08
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:2/5.5 VProp。Delay @ Nom-Sup:13 ns
传播延迟(tpd):10.5 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:1.25 mmBase Number Matches:1

74V1G126C 数据手册

 浏览型号74V1G126C的Datasheet PDF文件第2页浏览型号74V1G126C的Datasheet PDF文件第3页浏览型号74V1G126C的Datasheet PDF文件第4页浏览型号74V1G126C的Datasheet PDF文件第5页浏览型号74V1G126C的Datasheet PDF文件第6页浏览型号74V1G126C的Datasheet PDF文件第7页 
74V1G126  
SINGLE BUS BUFFER (3-STATE)  
PRELIMINARY DATA  
HIGH SPEED:tPD =3.8ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
ICC =1 µA (MAX.) at TA =25 oC  
HIGH NOISEIMMUNITY:  
VNIH = VNIL =28% VCC (MIN.)  
POWERDOWN PROTECTIONON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
S
C
(SOT23-5L)  
(SC-70)  
ORDER CODE:  
74V1G126S  
74V1G126C  
3-STATE control input G has to be set LOW to  
place the output into the high impedance state.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 5.5V  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The 74V1G125 is an advanced high-speed  
CMOS SINGLE BUS BUFFER fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
October 1999  

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