74V1G126S

更新时间： 2024-11-03 22:22:07

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
8页	59K
描述
SINGLE BUS BUFFER 3-STATE

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中文翻译

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数据手册

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74V1G126S 数据手册

74V1G126

SINGLE BUS BUFFER (3-STATE)

PRELIMINARY DATA

■

HIGH SPEED:t_PD=3.8ns (TYP.) atV_CC= 5V

LOW POWER DISSIPATION:

I_CC=1 µA (MAX.) at T_A=25 ^oC

HIGH NOISEIMMUNITY:

■

V_NIH= V_NIL=28% V_CC(MIN.)

POWERDOWN PROTECTIONON INPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

|I_OH| = I_OL= 8 mA (MIN)

BALANCEDPROPAGATIONDELAYS:

t_PLHt_PHL

■

(SOT23-5L)

(SC-70)

ORDER CODE:

74V1G126S

74V1G126C

■

3-STATE control input G has to be set LOW to

place the output into the high impedance state.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface5V to 3V.

OPERATING VOLTAGERANGE:

V_CC(OPR)= 2V to 5.5V

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74V1G125 is an advanced high-speed

CMOS SINGLE BUS BUFFER fabricated with

sub-micron silicon gate and double-layer metal

wiring C²MOS technology.

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/8

October 1999

12 3 4 5 6 7 8

中文翻译

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