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74V1G32S PDF预览

74V1G32S

更新时间: 2024-11-03 22:45:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
7页 51K
描述
SINGLE 2-INPUT OR GATE

74V1G32S 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOT-23
包装说明:SOT-23, 5 PIN针数:5
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.31Is Samacsys:N
系列:74VJESD-30 代码:R-PDSO-G5
JESD-609代码:e0长度:2.9 mm
负载电容(CL):50 pF逻辑集成电路类型:OR GATE
最大I(ol):0.004 A功能数量:1
输入次数:2端子数量:5
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:LSSOP
封装等效代码:TSOP5/6,.11,37封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/5.5 VProp。Delay @ Nom-Sup:13 ns
传播延迟(tpd):12 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.45 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.95 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.625 mmBase Number Matches:1

74V1G32S 数据手册

 浏览型号74V1G32S的Datasheet PDF文件第2页浏览型号74V1G32S的Datasheet PDF文件第3页浏览型号74V1G32S的Datasheet PDF文件第4页浏览型号74V1G32S的Datasheet PDF文件第5页浏览型号74V1G32S的Datasheet PDF文件第6页浏览型号74V1G32S的Datasheet PDF文件第7页 
74V1G32  
SINGLE 2-INPUT OR GATE  
HIGH SPEED:tPD =3.8ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
ICC =2 µA (MAX.) at TA =25 oC  
HIGH NOISEIMMUNITY:  
VNIH = VNIL =28% VCC (MIN.)  
S
C
POWERDOWN PROTECTIONON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
(SOT23-5L)  
(SC-70)  
ORDER CODE:  
74V1G32S  
74V1G32C  
The internal circuit is composed of 2 stages  
including buffer output, which provide high noise  
immunity and stable output.  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 5.5V  
IMPROVED LATCH-UP IMMUNITY  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
DESCRIPTION  
The 74V1G32 is an advanced high-speed CMOS  
SINGLE 2-INPUT OR GATE fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/7  
October 1999  

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