Datasheet > 74S1051

74S1051

更新时间： 2024-09-13 03:07:47

品牌	Logo	应用领域
德州仪器 - TI		二极管
页数	文件大小	规格书
13页	342K
描述
12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY

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74S1051 数据手册

SN74S1051

12-BIT SCHOTTKY BARRIER DIODE

BUS-TERMINATION ARRAY

SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003

D, N, NS, OR PW PACKAGE

(TOP VIEW)

Designed to Reduce Reflection Noise

Repetitive Peak Forward Current to 200 mA

12-Bit Array Structure Suited for

Bus-Oriented Systems

D12

D11

D10

D09

D08

D07

GND

D01

D02

D03

D04

D05

D06

GND

description/ordering information

This Schottky barrier diode bus-termination array

is designed to reduce reflection noise on memory

bus lines. This device consists of a 12-bit

high-speed Schottky diode array suitable for

clamping to V

and/or GND.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

PDIP – N

SOIC – D

Tube

SN74S1051N

Tube

SN74S1051D

S1051

0°C to 70°C

Tape and reel

SN74S1051DR

SN74S1051NSR

SN74S1051PWR

SOP – NS

74S1051

S1051

TSSOP – PW

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

schematic diagrams

D01 D02

D03 D04

D05 D06 D07 D08 D09

10 11 12

D10

D11

D12

GND GND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...13

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