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74LVX08_04 PDF预览

74LVX08_04

更新时间: 2024-11-11 04:47:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件
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11页 232K
描述
LOW VOLTAGE CMOS QUAD 2-INPUT AND GATE WITH 5V TOLERANT INPUTS

74LVX08_04 数据手册

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74LVX08  
LOW VOLTAGE CMOS QUAD 2-INPUT AND GATE  
WITH 5V TOLERANT INPUTS  
HIGH SPEED:  
= 4.8ns (TYP.) at V = 3.3V  
t
PD  
CC  
5V TOLERANT INPUTS  
INPUT VOLTAGE LEVEL:  
V =0.8V, V =2V AT V =3V  
IL  
IH  
CC  
LOW POWER DISSIPATION:  
= 2 µA (MAX.) at T =25°C  
SOP  
TSSOP  
I
CC  
A
LOW NOISE:  
= 0.3V (TYP.) at V = 3.3V  
V
Table 1: Order Codes  
PACKAGE  
OLP  
CC  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
T & R  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
SOP  
74LVX08MTR  
74LVX08TTR  
t
t
PLH  
PHL  
TSSOP  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
V
CC  
The internal circuit is composed of 2 stages  
including buffer output, which provides high noise  
immunity and stable output.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage.  
This device can be used to interface 5V to 3V  
system. It combines high speed performance with  
the true CMOS low power consumption. All inputs  
and outputs are equipped with protection circuits  
against static discharge, giving them 2KV ESD  
immunity and transient excess voltage.  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 08  
IMPROVED LATCH-UP IMMUNITY  
POWER DOWN PROTECTION ON INPUTS  
DESCRIPTION  
The 74LVX08 is a low voltage CMOS QUAD  
2-INPUT AND GATE fabricated with sub-micron  
silicon gate and double-layer metal wiring C MOS  
technology. It is ideal for low power, battery  
operated and low noise 3.3V applications.  
2
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 4  
1/11  
August 2004  

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