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74LVTH16374MEAX PDF预览

74LVTH16374MEAX

更新时间: 2024-11-13 20:15:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
8页 93K
描述
Bus Driver, LVT Series, 2-Func, 8-Bit, True Output, BICMOS, PDSO48, 0.300 INCH, MO-118, SSOP-48

74LVTH16374MEAX 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP48,.4
针数:48Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.02
系列:LVTJESD-30 代码:R-PDSO-G48
JESD-609代码:e3长度:15.875 mm
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:160000000 Hz
最大I(ol):0.064 A湿度敏感等级:1
位数:8功能数量:2
端口数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP48,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:4.5 ns传播延迟(tpd):5.2 ns
认证状态:Not Qualified座面最大高度:2.74 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.495 mm
Base Number Matches:1

74LVTH16374MEAX 数据手册

 浏览型号74LVTH16374MEAX的Datasheet PDF文件第2页浏览型号74LVTH16374MEAX的Datasheet PDF文件第3页浏览型号74LVTH16374MEAX的Datasheet PDF文件第4页浏览型号74LVTH16374MEAX的Datasheet PDF文件第5页浏览型号74LVTH16374MEAX的Datasheet PDF文件第6页浏览型号74LVTH16374MEAX的Datasheet PDF文件第7页 
January 1999  
Revised June 2002  
74LVT16374 74LVTH16374  
Low Voltage 16-Bit D-Type Flip-Flop  
with 3-STATE Outputs  
General Description  
Features  
Input and output interface capability to systems at  
The LVT16374 and LVTH16374 contain sixteen non-invert-  
ing D-type flip-flops with 3-STATE outputs and is intended  
for bus oriented applications. The device is byte controlled.  
A buffered clock (CP) and Output Enable (OE) are com-  
mon to each byte and can be shorted together for full 16-bit  
operation.  
5V VCC  
Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs (74LVTH16374),  
also available without bushold feature (74LVT16374)  
Live insertion/extraction permitted  
The LVTH16374 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
Power Up/Power Down high impedance provides  
glitch-free bus loading  
Outputs source/sink 32 mA/+64 mA  
Functionally compatible with the 74 series 16374  
Latch-up performance exceeds 500 mA  
ESD performance:  
These flip-flops are designed for low-voltage (3.3V) VCC  
applications, but with the capability to provide a TTL inter-  
face to a 5V environment. The LVT16374 and LVTH16374  
are fabricated with an advanced BiCMOS technology to  
achieve high speed operation similar to 5V ABT while  
maintaining a low power dissipation.  
Human-body model > 2000V  
Machine model > 200V  
Charged-device model > 1000V  
Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA)  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74LVT16374G  
BGA54A  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
(Note 1)(Note 2)  
(Preliminary)  
74LVT16374MEA  
(Note 2)  
MS48A  
MTD48  
BGA54A  
MS48A  
MTD48  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
74LVT16374MTD  
(Note 2)  
74LVTH16374G  
(Note 1)(Note 2)  
74LVTH16374MEA  
(Note 2)  
74LVTH16374MTD  
(Note 2)  
Note 1: Ordering code “G” indicates Trays.  
Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
© 2002 Fairchild Semiconductor Corporation  
DS012022  
www.fairchildsemi.com  

74LVTH16374MEAX 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVTH16374DL TI

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3.3 V ABT 16BIT EDGE - TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS

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