74LVTH16543MTD

更新时间： 2024-11-17 22:56:23

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
页数	文件大小	规格书
8页	79K
描述
Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs

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中文翻译

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数据手册
替代型号

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74LVTH16543MTD 数据手册

January 2000

Revised October 2001

74LVT16543 • 74LVTH16543

Low Voltage 16-Bit Registered Transceiver

with 3-STATE Outputs

General Description

Features

■ Input and output interface capability to systems at

The LVT16543 and LVTH16543 16-bit transceivers

contain two sets of D-type latches for temporary storage of

data flowing in either direction. Separate Latch Enable and

Output Enable inputs are provided for each register to per-

mit independent control of inputting and outputting in either

direction of data flow. Each byte has separate control

inputs, which can be shorted together for full 16-bit opera-

tion.

5V V_CC

■ Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH16543)

■ Also available without bushold feature (74LVT16543)

■ Live insertion/extraction permitted

■ Power Up/Down high impedance provides glitch-free

bus loading

The LVTH16543 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

■ Outputs source/sink −32 mA/+64 mA

■ Functionally compatible with the 74 series 16543

■ Latch-up conforms to JEDEC JED78

■ ESD performance:

These transceivers are designed for low-voltage (3.3V)

V_CCapplications, but with the capability to provide a TTL

interface to

a 5V environment. The LVT16543 and

Human-body model > 2000V

LVTH16543 are fabricated with an advanced BiCMOS

technology to achieve high speed operation similar to 5V

ABT while maintaining low power dissipation.

Machine model > 200V

Charged-device model > 1000V

Ordering Code:

Order Number

Package Number

Package Description

74LVT16543MEA

(Preliminary)

MS56A

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LVT16543MTD

(Preliminary)

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

74LVTH16543MEA

74LVTH16543MTD

MS56A

MTD56

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

DS012449

www.fairchildsemi.com

12 3 4 5 6 7 8

中文翻译

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74LVTH16543MTD 替代型号

型号	品牌	替代类型	描述	数据表
74LVTH16543MTDX	FAIRCHILD	完全替代	Dual 8-bit Bus Transceiver
SN74LVTH16543DGGR	TI	功能相似	3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
74LVTH16543DGGRE4	TI	功能相似	3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

与74LVTH16543MTD相关器件

型号	品牌	获取价格	描述	数据表
74LVTH16543MTD_NL	FAIRCHILD	获取价格	Registered Bus Transceiver, LVT Series, 2-Func, 8-Bit, True Output, BICMOS, PDSO56, 6.10 M
74LVTH16543MTDX	FAIRCHILD	获取价格	Dual 8-bit Bus Transceiver
74LVTH16543MTDX_NL	FAIRCHILD	获取价格	Registered Bus Transceiver, LVT Series, 2-Func, 8-Bit, True Output, BICMOS, PDSO56, 6.10 M
74LVTH16646	FAIRCHILD	获取价格	Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
74LVTH16646DGGRE4	TI	获取价格	3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
74LVTH16646DLRG4	TI	获取价格	3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
74LVTH16646MEA	FAIRCHILD	获取价格	Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
74LVTH16646MEAX	ETC	获取价格	Dual 8-bit Bus Transceiver
74LVTH16646MTD	FAIRCHILD	获取价格	Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
74LVTH16646MTDX	ONSEMI	获取价格	带3态输出的低电压16位收发器/寄存器

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