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74LVTH16543DLRG4 PDF预览

74LVTH16543DLRG4

更新时间： 2024-11-19 21:54:35
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
12页 205K
描述
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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74LVTH16543DLRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP, SSOP56,.4针数：56
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.28其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：LVTJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：18.415 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.064 A湿度敏感等级：1
位数：8功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP56,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：5 mAProp。Delay @ Nom-Sup：3.2 ns
传播延迟（tpd）：4.9 ns认证状态：Not Qualified
座面最大高度：2.79 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：7.49 mm

74LVTH16543DLRG4 数据手册

 浏览型号74LVTH16543DLRG4的Datasheet PDF文件第2页浏览型号74LVTH16543DLRG4的Datasheet PDF文件第3页浏览型号74LVTH16543DLRG4的Datasheet PDF文件第4页浏览型号74LVTH16543DLRG4的Datasheet PDF文件第5页浏览型号74LVTH16543DLRG4的Datasheet PDF文件第6页浏览型号74LVTH16543DLRG4的Datasheet PDF文件第7页 
SN54LVTH16543, SN74LVTH16543  
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS699D – JULY 1997 – REVISED APRIL 1999  
SN54LVTH16543 . . . WD PACKAGE  
SN74LVTH16543 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
1OEAB  
1LEAB  
1CEAB  
GND  
1OEBA  
1LEBA  
1CEBA  
GND  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
2
3
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
4
)
1A1  
1B1  
5
CC  
1A2  
1B2  
6
Support Unregulated Battery Operation  
Down to 2.7 V  
V
V
7
CC  
CC  
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
8
I
and Power-Up 3-State Support Hot  
off  
9
Insertion  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
Flow-Through Architecture Optimizes PCB  
Layout  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
V
V
CC  
CC  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
2A7  
2A8  
GND  
2CEAB  
2LEAB  
2OEAB  
2B7  
2B8  
GND  
2CEBA  
2LEBA  
2OEBA  
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
The ’LVTH16543 devices are 16-bit registered transceivers designed for low-voltage (3.3-V)V operation, but  
CC  
with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two  
8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB  
or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.  
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and  
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches  
inthestoragemode. WithCEABandOEABbothlow, the3-stateBoutputsareactiveandreflectthedatapresent  
at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA  
inputs.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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74LVTH16543DLRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVTH16543DLG4 TI

完全替代

 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVTH16543DLR TI

完全替代

 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVTH16543DL TI

完全替代

 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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74LVTH16543MTD FAIRCHILD

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74LVTH16646DGGRE4 TI

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74LVTH16646DLRG4 TI

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