74LVTH16500

更新时间： 2024-09-24 22:56:23

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线收发器
页数	文件大小	规格书
7页	70K
描述
Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary

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74LVTH16500 数据手册

Preliminary

May 2000

Revised May 2000

74LVTH16500

Low Voltage 18-Bit Universal Bus Transceivers

with 3-STATE Outputs (Preliminary)

General Description

The LVTH16500 is an 18-bit universal bus transceiver

combining D-type latches and D-type flip-flops to allow

data flow in transparent, latched, and clocked modes.

Features

■ Input and output interface capability to systems at

5V V_CC

■ Bushold data inputs eliminate the need for external

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs.

pull-up resistors to hold unused inputs

■ Live insertion/extraction permitted

■ Power Up/Down high impedance provides glitch-free

bus loading

The LVTH16500 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

■ Outputs source/sink −32 mA/+64 mA

■ Functionally compatible with the 74 series 16500

■ Latch-up performance exceeds 500 mA

The transceiver is designed for low voltage (3.3V) V_CC

applications, but with the capability to provide a TTL inter-

face to a 5V environment. The LVTH16500 is fabricated

with an advanced BiCMOS technology to achieve high

speed operation similar to 5V ABT while maintaining low

power dissipation.

Ordering Code:

Order Number

74LVTH16500MEA

74LVTH16500MTD

Package Number

MS56A

Package Description

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

MTD56

Devices also available in Tape and Reel. Specify by appending the suffix “X” to the ordering code.

DS012447

www.fairchildsemi.com

12 3 4 5 6 7

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