74LVTH16501MEAX_NL

更新时间： 2024-11-18 13:04:59

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线收发器
页数	文件大小	规格书
7页	67K
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74LVTH16501MEAX_NL 数据手册

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March 2001

Revised March 2001

74LVTH16501

Low Voltage 18-Bit Universal Bus Transceivers

with Bushold and 3-STATE Outputs

General Description

The LVTH16501 is an 18-bit universal bus transceiver

combining D-type latches and D-type flip-flops to allow

data flow in transparent, latched, and clocked modes.

Features

■ Input and output interface capability to systems at

5V V_CC

■ Bushold data inputs eliminate the need for external

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs.

pull-up resistors to hold unused inputs

■ Live insertion/extraction permitted

■ Power up/down high impedance provides glitch-free bus

The LVTH16501 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

■ Outputs source/sink −32 mA/+64 mA

■ Functionally compatible with the 74 series 16501

■ ESD Performance:

The transceiver is designed for low voltage (3.3V) V_CC

applications, but with the capability to provide a TTL inter-

face to a 5V environment. The LVTH16501 is fabricated

with an advanced BiCMOS technology to achieve high

speed operation similar to 5V ABT while maintaining low

power dissipation.

Human-Body Model > 2000V

Machine Model > 200V

Charged-Device Model > 1000V

Ordering Code:

Order Number

74LVTH16501MEA

74LVTH16501MTD

Package Number

MS56A

Package Description

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

MTD56

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

DS500101

www.fairchildsemi.com

12 3 4 5 6 7

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