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74LVQ32_04 PDF预览

74LVQ32_04

更新时间: 2024-11-18 04:47:51
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意法半导体 - STMICROELECTRONICS 输入元件
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11页 230K
描述
LOW VOLTAGE CMOS QUAD 2-INPUT OR GATE

74LVQ32_04 数据手册

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74LVQ32  
LOW VOLTAGE CMOS QUAD 2-INPUT OR GATE  
HIGH SPEED:  
= 5.2 ns (TYP.) at V = 3.3 V  
t
PD  
CC  
COMPATIBLE WITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
I
= 2µA (MAX.) at T =25°C  
CC  
A
LOW NOISE:  
= 0.3V (TYP.) at V = 3.3V  
75TRANSMISSION LINE DRIVING  
CAPABILITY  
SOP  
TSSOP  
V
OLP  
CC  
Table 1: Order Codes  
PACKAGE  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 12mA (MIN) at V = 3.0V  
OH  
OL  
CC  
T & R  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
SOP  
74LVQ32MTR  
74LVQ32TTR  
TSSOP  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 32  
V
technology. It is ideal for low power and low noise  
3.3V applications.  
The internal circuit is composed of 2 stages  
including buffer output, which enables high noise  
immunity and stable output.  
CC  
IMPROVED LATCH-UP IMMUNITY  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74LVQ32 is a low voltage CMOS QUAD  
2-INPUT OR GATE fabricated with sub-micron  
2
silicon gate and double-layer metal wiring C MOS  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 5  
1/11  
July 2004  

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