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74LVQ373_04 PDF预览

74LVQ373_04

更新时间: 2024-11-18 04:47:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输出元件
页数 文件大小 规格书
13页 292K
描述
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING

74LVQ373_04 数据手册

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74LVQ373  
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUTS NON INVERTING  
HIGH SPEED:  
= 5.8 ns (TYP.) at V = 3.3 V  
t
PD  
CC  
COMPATIBLE WITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
I
= 4 µA (MAX.) at T =25°C  
A
CC  
LOW NOISE:  
= 0.4V (TYP.) at V = 3.3V  
75TRANSMISSION LINE OUTPUT DRIVE  
CAPABILITY  
V
OLP  
CC  
SOP  
TSSOP  
Table 1: Order Codes  
PACKAGE  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 12mA (MIN) at V = 3.0 V  
OH  
OL  
CC  
T & R  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
SOP  
74LVQ373MTR  
74LVQ373TTR  
t
t
PHL  
TSSOP  
PLH  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 373  
V
enable input (LE) and an output enable input (OE).  
While the LE inputs is held at a high level, the Q  
outputs will follow the data input precisely.  
When the LE is taken low, the Q outputs will be  
latched precisely at the logic level of D input data.  
While the (OE) input is low, the 8 outputs will be in  
a normal logic state (high or low logic level) and  
while high level the outputs will be in a high  
impedance state.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
CC  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The 74LVQ373 is a low voltage CMOS OCTAL  
D-TYPE LATCH with 3 STATE OUTPUT NON  
INVERTING fabricated with sub-micron silicon  
gate and double-layer metal wiring C MOS  
technology. It is ideal for low power and low noise  
3.3V applications.  
2
These 8 bit D-Type latch are controlled by a latch  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 5  
1/13  
July 2004  

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