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74LVQ374_01 PDF预览

74LVQ374_01

更新时间: 2024-11-21 04:47:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
13页 293K
描述
Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

74LVQ374_01 数据手册

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74LVQ374  
OCTAL D-TYPE FLIP-FLOP  
WITH 3 STATE OUTPUTS NON INVERTING  
HIGH SPEED:  
= 180 MHz (TYP.) at V = 3.3V  
f
MAX  
CC  
COMPATIBLE WITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
I
= 4µA (MAX.) at T =25°C  
CC  
A
LOW NOISE:  
= 0.4V (TYP.) at V = 3.3V  
75TRANSMISSION LINE DRIVING  
CAPABILITY  
V
SOP  
TSSOP  
OLP  
CC  
Table 1: Order Codes  
PACKAGE  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 12 mA (MIN) at V = 3.0V  
OH  
OL  
CC  
T & R  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
SOP  
74LVQ374MTR  
74LVQ374TTR  
t
t
PHL  
TSSOP  
PLH  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 374  
V
outputs will be set to the logic that were setup at  
the D inputs.  
While the (OE) input is low, the 8 outputs will be in  
a normal logic state (high or low logic level) and  
while high level the outputs will be in a high  
impedance state.  
CC  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The output control does not affect the internal  
operation of flip-flops; that is, the old data can be  
retained or the new data can be entered even  
while the outputs are off.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
74LVQ374 is a low voltage CMOS OCTAL  
D-TYPE FLIP-FLOP with 3 STATE OUTPUTS  
NON INVERTING fabricated with sub-micron  
silicon gate and double-layer metal wiring C MOS  
technology. It is ideal for low power and low noise  
3.3V applications.  
These 8 bit D-Type Flip-Flops are controlled by a  
clock input (CK) and an output enable input (OE).  
On the positive transition of the clock, the Q  
2
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 5  
1/13  
July 2004  

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