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74LVQ374SCX PDF预览

74LVQ374SCX

更新时间: 2024-11-20 23:24:27
品牌 Logo 应用领域
其他 - ETC 触发器
页数 文件大小 规格书
7页 74K
描述
Octal D-Type Flip-Flop

74LVQ374SCX 数据手册

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February 1992  
Revised June 2001  
74LVQ374  
Low Voltage Octal D-Type Flip-Flop  
with 3-STATE Outputs  
General Description  
Features  
Ideal for low power/low noise 3.3V applications  
The LVQ374 is a high-speed, low-power octal D-type flip-  
flop featuring separate D-type inputs for each flip-flop and  
3-STATE outputs for bus-oriented applications. A buffered  
Clock (CP) and Output Enable (OE) are common to all flip-  
flops.  
Implements patented EMI reduction circuitry  
Available in SOIC JEDEC, SOIC EIAJ and QSOP pack-  
ages  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Improved latch-up immunity  
Guaranteed incident wave switching into 75  
4 kV minimum ESD immunity  
Buffered positive edge-triggered clock  
3-STATE outputs drive bus lines or buffer memory  
address registers  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVQ374SC  
74LVQ374SJ  
74LVQ374QSC  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
MQA20  
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Truth Table  
Inputs  
Outputs  
Pin Descriptions  
Dn  
H
L
CP  
OE  
L
On  
H
L
Pin Names  
Description  
D0D7  
CP  
Data Inputs  
Clock Pulse Input  
L
X
X
H
Z
H = HIGH Voltage Level  
X = Immaterial  
= LOW-to-HIGH Transition  
L = LOW Voltage Level  
Z = High Impedance  
OE  
3-STATE Output Enable Input  
3-STATE Outputs  
O0O7  
© 2001 Fairchild Semiconductor Corporation  
DS011360  
www.fairchildsemi.com  

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