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74LVQ373QSCX PDF预览

74LVQ373QSCX

更新时间: 2024-11-17 22:14:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器逻辑集成电路光电二极管输出元件驱动
页数 文件大小 规格书
7页 73K
描述
Low Voltage Octal Transparent Latch with 3-STATE Outputs

74LVQ373QSCX 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:0.150 INCH, MO-137, QSOP-20
针数:20Reach Compliance Code:unknown
风险等级:5.47系列:LVQ
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:11 ns
传播延迟(tpd):18 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9116 mm
Base Number Matches:1

74LVQ373QSCX 数据手册

 浏览型号74LVQ373QSCX的Datasheet PDF文件第2页浏览型号74LVQ373QSCX的Datasheet PDF文件第3页浏览型号74LVQ373QSCX的Datasheet PDF文件第4页浏览型号74LVQ373QSCX的Datasheet PDF文件第5页浏览型号74LVQ373QSCX的Datasheet PDF文件第6页浏览型号74LVQ373QSCX的Datasheet PDF文件第7页 
February 1992  
Revised June 2001  
74LVQ373  
Low Voltage Octal Transparent Latch  
with 3-STATE Outputs  
General Description  
Features  
Ideal for low power/low noise 3.3V applications  
The LVQ373 consists of eight latches with 3-STATE out-  
puts for bus organized system applications. The latches  
appear transparent to the data when Latch Enable (LE) is  
HIGH. When LE is low, the data satisfying the input timing  
requirements is latched. Data appears on the bus when the  
Output Enable (OE) is LOW. When OE is HIGH, the bus  
output is in the high impedance state.  
Implements patented EMI reduction circuitry  
Available in SOIC JEDEC, SOIC EIAJ and QSOP  
packages  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Improved latch-up immunity  
Guaranteed incident wave switching into 75  
4 kV minimum ESD immunity  
Ordering Code:  
Order Number  
74LVQ373SC  
74LVQ373SJ  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide  
M20D  
74LVQ373QSC  
MQA20  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Truth Table  
Inputs  
Outputs  
On  
Pin Descriptions  
LE  
OE  
Dn  
X
H
H
L
H
L
L
L
X
L
Z
L
Pin Names  
Description  
D0D7  
LE  
Data Inputs  
H
X
H
Latch Enable Input  
O0  
OE  
Output Enable Input  
3-STATE Latch Outputs  
H = HIGH Voltage Level  
Z = High Impedance  
L = LOW Voltage Level  
X = Immaterial  
O0O7  
O
0 = Previous O0 before HIGH to Low transition of Latch Enable  
© 2001 Fairchild Semiconductor Corporation  
DS011359  
www.fairchildsemi.com  

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