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74LVQ373SJ PDF预览

74LVQ373SJ

更新时间: 2024-11-17 22:53:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
7页 73K
描述
Low Voltage Octal Transparent Latch with 3-STATE Outputs

74LVQ373SJ 数据手册

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February 1992  
Revised June 2001  
74LVQ373  
Low Voltage Octal Transparent Latch  
with 3-STATE Outputs  
General Description  
Features  
Ideal for low power/low noise 3.3V applications  
The LVQ373 consists of eight latches with 3-STATE out-  
puts for bus organized system applications. The latches  
appear transparent to the data when Latch Enable (LE) is  
HIGH. When LE is low, the data satisfying the input timing  
requirements is latched. Data appears on the bus when the  
Output Enable (OE) is LOW. When OE is HIGH, the bus  
output is in the high impedance state.  
Implements patented EMI reduction circuitry  
Available in SOIC JEDEC, SOIC EIAJ and QSOP  
packages  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Improved latch-up immunity  
Guaranteed incident wave switching into 75  
4 kV minimum ESD immunity  
Ordering Code:  
Order Number  
74LVQ373SC  
74LVQ373SJ  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide  
M20D  
74LVQ373QSC  
MQA20  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Truth Table  
Inputs  
Outputs  
On  
Pin Descriptions  
LE  
OE  
Dn  
X
H
H
L
H
L
L
L
X
L
Z
L
Pin Names  
Description  
D0D7  
LE  
Data Inputs  
H
X
H
Latch Enable Input  
O0  
OE  
Output Enable Input  
3-STATE Latch Outputs  
H = HIGH Voltage Level  
Z = High Impedance  
L = LOW Voltage Level  
X = Immaterial  
O0O7  
O
0 = Previous O0 before HIGH to Low transition of Latch Enable  
© 2001 Fairchild Semiconductor Corporation  
DS011359  
www.fairchildsemi.com  

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