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74LVQ373 PDF预览

74LVQ373

更新时间: 2024-11-17 22:53:19
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输出元件
页数 文件大小 规格书
10页 77K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING

74LVQ373 数据手册

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74LVQ373  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUTS NON INVERTING  
HIGH SPEED:tPD =6 ns (TYP.) atVCC =3.3V  
COMPATIBLEWITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
o
µ
I
CC =4 A (MAX.) at TA =25 C  
LOWNOISE:VOLP = 0.4V(TYP.) at VCC =3.3V  
75TRANSMISSIONLINEOUTPUT DRIVE  
CAPABILITY  
M
T
(Micro Package)  
(TSSOPPackage)  
ORDER CODES :  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 12 mA (MIN)  
74LVQ373M  
74LVQ373T  
PCI BUSLEVELSGUARANTEED AT 24mA  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
input (OE).  
While the LE input is held at a high level, the Q  
outputswill follow the data input precisely.  
When the LE is taken low, the Q outputs will be  
latched precisely at the logic level of D input data.  
While the (OE) input is low, the 8 outputs will be  
in a normal logic state (high or low logic level)  
and while high level the outputs will be in a high  
impedance state.  
It has better speed performance at 3.3V than 5V  
LS-TTL family combined with the true CMOS low  
power consuption.  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 3.6V (1.2VData Retention)  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES373  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The LVQ373 is a low voltage CMOS OCTAL  
D-TYPE LATCH with 3 STATE OUTPUTS NON  
INVERTING fabricated with sub-micron silicon  
gate and double-layer metal wiring C2MOS  
technology.It is ideal for low power and low noise  
3.3V applications.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
These 8 bit D-Type latchs are controlled by a  
latch enable input (LE) and an output enable  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/10  
February 1999  

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