74LVQ299

更新时间： 2024-11-18 04:47:51

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		移位寄存器
页数	文件大小	规格书
15页	460K
描述
8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR

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中文翻译

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数据手册

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74LVQ299 数据手册

74LVQ299

8 BIT PIPO SHIFT REGISTER

WITH ASYNCHRONOUS CLEAR

■

HIGH SPEED:

= 8.3 ns (TYP.) at V = 3.3 V

■

COMPATIBLE WITH TTL OUTPUTS

LOW POWER DISSIPATION:

= 4 µA (MAX.) at T =25°C

■

LOW NOISE:

= 0.5V (TYP.) at V = 3.3V

SOP

TSSOP

OLP

75Ω TRANSMISSION LINE DRIVING

CAPABILITY

Table 1: Order Codes

PACKAGE

SYMMETRICAL OUTPUT IMPEDANCE:

T & R

|I | = I = 12mA (MIN) at V = 3.0 V

SOP

74LVQ299MTR

74LVQ299TTR

■

PCI BUS LEVELS GUARANTEED AT 24 mA

BALANCED PROPAGATION DELAYS:

TSSOP

PLH

PHL

These devices have four modes (HOLD, SHIFT

LEFT, SHIFT RIGHT and LOAD DATA). Each

mode is chosen by two function select inputs (S0,

S1) as shown in the Truth Table.

When one or both enable inputs, (G1, G2) are

high, the eight input/output terminals are in the

high impedance state; however sequential

operation or clearing of the register is not affected.

Clear function is asynchronous to clock.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

■

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 3.6V (1.2V Data Retention)

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 299

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74LVQ299 is a low voltage CMOS 8 BIT

PIPO SHIFT REGISTER (3-STATE) fabricated

with sub-micron silicon gate and double-layer

metal wiring C MOS technology. It is ideal for low

power and low noise 3.3V applications.

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 2

1/15

July 2004

12 3 4 5 6 7...15

中文翻译

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与74LVQ299相关器件

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