74LVQ280

更新时间： 2024-11-17 22:53:19

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
8页	232K
描述
9 BIT PARITY GENERATOR

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中文翻译

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数据手册

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74LVQ280 数据手册

74LVQ280

9 BIT PARITY GENERATOR

■

HIGH SPEED:

= 8 ns (TYP.) at V = 3.3 V

■

COMPATIBLE WITH TTL OUTPUTS

LOW POWER DISSIPATION:

= 2µA(MAX.) at T =25°C

■

LOW NOISE:

= 0.3V (TYP.) at V = 3.3V

75Ω TRANSMISSION LINE DRIVING

CAPABILITY

SYMMETRICAL OUTPUT IMPEDANCE:

SOP

TSSOP

OLP

ORDER CODES

PACKAGE

|I | = I = 12mA (MIN) at V = 3.0 V

TUBE

T & R

■

PCI BUS LEVELS GUARANTEED AT 24 mA

BALANCED PROPAGATION DELAYS:

SOP

74LVQ280M

74LVQ280MTR

74LVQ280TTR

TSSOP

PHL

PLH

■

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 3.6V

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 280

data inputs control the output conditions. When

the number of high level input is odd, ΣODD

output is kept high and ΣEVEN output low.

Conversely, when the number of high level is

even, ΣEVEN output is kept high and ΣODD low.

The IC generates either odd or even parity making

it flexible application. The word-length capability is

easily expanded by cascading.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74LVQ280 is a low voltage CMOS 9 BIT

PARITY GENERATOR fabricated with sub-micron

silicon gate and double-layer metal wiring C MOS

technology. It is ideal for low power and low noise

3.3V applications.

It is composed of nine data inputs (A to I) and odd/

even parity outputs (ΣODD and ΣEVEN). The nine

PIN CONNECTION AND IEC LOGIC SYMBOLS

July 2001

1/8

12 3 4 5 6 7 8

中文翻译

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