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74LVC2G241DP,118 PDF预览

74LVC2G241DP,118

更新时间: 2024-11-16 14:47:07
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
23页 291K
描述
74LVC2G241 - Dual buffer/line driver; 3-state TSSOP 8-Pin

74LVC2G241DP,118 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP8,.16针数:8
Reach Compliance Code:unknown风险等级:5.54
其他特性:OUTPUT ENABLE ACTIVE HIGH FOR ONE FUNCTION控制类型:ENABLE LOW/HIGH
系列:LVC/LCX/ZJESD-30 代码:S-PDSO-G8
JESD-609代码:e4长度:3 mm
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:1位数:1
功能数量:2端口数量:2
端子数量:8最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.16
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL电源:3.3 V
Prop。Delay @ Nom-Sup:5.4 ns传播延迟(tpd):11 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):2.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:3 mm
Base Number Matches:1

74LVC2G241DP,118 数据手册

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74LVC2G241  
Dual buffer/line driver; 3-state  
Rev. 13 — 8 April 2013  
Product data sheet  
1. General description  
The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The  
3-state outputs are controlled by the output enable inputs 1OE and 2OE:  
A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state.  
A LOW level at pin 2OE causes output 2Y to assume a high-impedance OFF-state.  
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and  
fall times.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the  
74LVC2G241 as a translator in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing a damaging backflow current through the device  
when it is powered down.  
2. Features and benefits  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant input/output for interfacing with 5 V logic  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C  
 
 

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