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74LVC2G32DC-Q100 PDF预览

74LVC2G32DC-Q100

更新时间: 2024-10-02 01:14:39
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
14页 786K
描述
Dual 2-input OR gate

74LVC2G32DC-Q100 数据手册

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74LVC2G32-Q100  
Dual 2-input OR gate  
Rev. 2 — 14 December 2016  
Product data sheet  
1. General description  
The 74LVC2G32-Q100 provides a 2-input OR gate function.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these  
devices as translators in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing a damaging backflow current through the device  
when it is powered down.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant outputs in the Power-down mode  
High noise immunity  
24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V)  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  

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