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74LVC2G14GW,125 PDF预览

74LVC2G14GW,125

更新时间: 2024-01-02 12:15:37
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
20页 144K
描述
74LVC2G14 - Dual inverting Schmitt trigger with 5 V tolerant input TSSOP 6-Pin

74LVC2G14GW,125 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:TSSOP包装说明:TSSOP, TSSOP6,.08
针数:6Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:3.5系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G6JESD-609代码:e3
长度:2 mm逻辑集成电路类型:INVERTER
最大I(ol):0.024 A湿度敏感等级:1
功能数量:2输入次数:1
端子数量:6最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP6,.08
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:3.3 V传播延迟(tpd):12 ns
认证状态:Not Qualified施密特触发器:YES
座面最大高度:1.1 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:1.25 mm
Base Number Matches:1

74LVC2G14GW,125 数据手册

 浏览型号74LVC2G14GW,125的Datasheet PDF文件第2页浏览型号74LVC2G14GW,125的Datasheet PDF文件第3页浏览型号74LVC2G14GW,125的Datasheet PDF文件第4页浏览型号74LVC2G14GW,125的Datasheet PDF文件第5页浏览型号74LVC2G14GW,125的Datasheet PDF文件第6页浏览型号74LVC2G14GW,125的Datasheet PDF文件第7页 
74LVC2G14  
Dual inverting Schmitt trigger with 5 V tolerant input  
Rev. 7 — 30 November 2011  
Product data sheet  
1. General description  
The 74LVC2G14 provides two inverting buffers with Schmitt-trigger input. It is capable of  
transforming slowly changing input signals into sharply defined, jitter-free output signals.  
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of  
this device in a mixed 3.3 V and 5 V environment. Schmitt-trigger action at the inputs  
makes the circuit tolerant of slower input rise and fall time. This device is fully specified for  
partial power-down applications using IOFF. The IOFF circuitry disables the output,  
preventing the damaging backflow current through the device when it is powered down.  
2. Features and benefits  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant inputs for interfacing with 5 V logic  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Unlimited rise and fall times  
Input accepts voltages up to 5 V  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C.  
3. Applications  
Wave and pulse shaper  
Astable multivibrator  
Monostable multivibrator  
 
 
 

74LVC2G14GW,125 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC2G14DCKTG4 TI

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DUAL SCHMITT-TRIGGER INVERTER
SN74LVC2G14DCKRE4 TI

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DUAL SCHMITT-TRIGGER INVERTER

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