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74LVC1G57 PDF预览

74LVC1G57

更新时间: 2024-11-17 21:58:07
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
18页 96K
描述
Low-power configurable multiple function gate

74LVC1G57 数据手册

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74LVC1G57  
Low-power configurable multiple function gate  
Rev. 01 — 6 September 2004  
Product data sheet  
1. General description  
The 74LVC1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device,  
superior to most advanced CMOS compatible TTL families.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this  
device in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry  
disables the output, preventing the damaging backflow current through the device when it  
is powered down.  
The 74LVC1G57 provides configurable multiple functions. The output state is determined  
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,  
NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND.  
All inputs (A, B and C) have Schmitt-trigger action. They are capable of transforming  
slowly changing input signals into sharply defined, jitter-free output signals.  
2. Features  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant input/output for interfacing with 5 V logic  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V).  
±24 mA output drive (VCC = 3.0 V)  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C.  

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