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74LVC1G57GM,115 PDF预览

74LVC1G57GM,115

更新时间: 2024-01-16 07:45:28
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
20页 149K
描述
74LVC1G57 - Low-power configurable multiple function gate SON 6-Pin

74LVC1G57GM,115 技术参数

是否Rohs认证:符合生命周期:Transferred
零件包装代码:SON包装说明:VSON, SOLCC6,.04,20
针数:6Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.13
Is Samacsys:N系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-N6JESD-609代码:e3
长度:1.45 mm负载电容(CL):50 pF
逻辑集成电路类型:LOGIC CIRCUIT最大I(ol):0.024 A
湿度敏感等级:1功能数量:1
端子数量:6最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:VSON封装等效代码:SOLCC6,.04,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:7.9 ns
认证状态:Not Qualified施密特触发器:YES
座面最大高度:0.5 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:1 mm
Base Number Matches:1

74LVC1G57GM,115 数据手册

 浏览型号74LVC1G57GM,115的Datasheet PDF文件第2页浏览型号74LVC1G57GM,115的Datasheet PDF文件第3页浏览型号74LVC1G57GM,115的Datasheet PDF文件第4页浏览型号74LVC1G57GM,115的Datasheet PDF文件第5页浏览型号74LVC1G57GM,115的Datasheet PDF文件第6页浏览型号74LVC1G57GM,115的Datasheet PDF文件第7页 
74LVC1G57  
Low-power configurable multiple function gate  
Rev. 6 — 6 December 2011  
Product data sheet  
1. General description  
The 74LVC1G57 provides configurable multiple functions. The output state is determined  
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,  
NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this  
device in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
All inputs (A, B and C) are Schmitt trigger inputs. They are capable of transforming slowly  
changing input signals into sharply defined, jitter-free output signals.  
2. Features and benefits  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant input/output for interfacing with 5 V logic  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V).  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C.  
 
 

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