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74LVC1G11GF/S500,132 PDF预览

74LVC1G11GF/S500,132

更新时间: 2024-11-20 14:50:03
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路
页数 文件大小 规格书
18页 200K
描述
AND Gate, LVC/LCX/Z Series, 1-Func, 3-Input, CMOS, PDSO6

74LVC1G11GF/S500,132 技术参数

生命周期:Active包装说明:VSON,
Reach Compliance Code:unknown风险等级:5.57
系列:LVC/LCX/ZJESD-30 代码:S-PDSO-N6
长度:1 mm逻辑集成电路类型:AND GATE
功能数量:1输入次数:3
端子数量:6最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:VSON封装形状:SQUARE
封装形式:SMALL OUTLINE, VERY THIN PROFILE传播延迟(tpd):21.5 ns
座面最大高度:0.5 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:NO LEAD
端子节距:0.35 mm端子位置:DUAL
宽度:1 mmBase Number Matches:1

74LVC1G11GF/S500,132 数据手册

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74LVC1G11  
Single 3-input AND gate  
Rev. 8 — 17 September 2015  
Product data sheet  
1. General description  
The 74LVC1G11 provides a single 3-input AND gate.  
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of  
this device in a mixed 3.3 V and 5 V environment.  
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and  
fall time.  
This device is fully specified for partial power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
2. Features and benefits  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant inputs for interfacing with 5 V logic  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V)  
24 mA output drive (VCC = 3.0 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C  

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