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74LVC1G11GW PDF预览

74LVC1G11GW

更新时间: 2024-11-19 22:00:55
品牌 Logo 应用领域
恩智浦 - NXP 栅极逻辑集成电路光电二极管
页数 文件大小 规格书
14页 70K
描述
Single 3-input AND gate

74LVC1G11GW 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOT-363
包装说明:PLASTIC, SOT-363, SC-88, 6 PIN针数:6
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.11
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G6
JESD-609代码:e3长度:2 mm
负载电容(CL):50 pF逻辑集成电路类型:AND GATE
最大I(ol):0.024 A湿度敏感等级:1
功能数量:1输入次数:3
端子数量:6最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP6,.08
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:6.2 ns
传播延迟(tpd):21.5 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.1 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:1.25 mmBase Number Matches:1

74LVC1G11GW 数据手册

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74LVC1G11  
Single 3-input AND gate  
Rev. 01 — 30 November 2004  
Product data sheet  
1. General description  
The 74LVC1G11 is a high-performance, low-voltage, Si-gate CMOS device and superior  
to most advanced CMOS compatible TTL families.  
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of  
this device in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry  
disables the output, preventing the damaging backflow current through the device when  
it is powered down.  
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and  
fall times.  
The 74LVC1G11 provides a single 3-input AND gate.  
2. Features  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant inputs for interfacing with 5 V logic  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V).  
±24 mA output drive (VCC = 3.0 V)  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C.  

74LVC1G11GW 替代型号

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