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74LVC1G11GS

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74LVC1G11GS 数据手册

74LVC1G11

Single 3-input AND gate

Rev. 7 — 4 July 2012

Product data sheet

1. General description

The 74LVC1G11 provides a single 3-input AND gate.

The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of

this device in a mixed 3.3 V and 5 V environment.

Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and

fall time.

This device is fully specified for partial power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V

 5 V tolerant inputs for interfacing with 5 V logic

 High noise immunity

 Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD8-B/JESD36 (2.7 V to 3.6 V)

 24 mA output drive (V_CC= 3.0 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 CMOS low power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C

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型号	品牌	获取价格	描述	数据表
74LVC1G11GV	NXP	获取价格	Single 3-input AND gate
74LVC1G11GV	NEXPERIA	获取价格	Single 3-input AND gateProduction
74LVC1G11GV,125	NXP	获取价格	74LVC1G11 - Single 3-input AND gate TSOP 6-Pin
74LVC1G11GV-Q100	NXP	获取价格	LVC/LCX/Z SERIES, 3-INPUT AND GATE, PDSO6, PLASTIC, SC-74, SOT-457, TSOP-6
74LVC1G11GV-Q100	NEXPERIA	获取价格	Single 3-input AND gate
74LVC1G11GV-Q100,125	NXP	获取价格	AND Gate, LVC/LCX/Z Series, 1-Func, 3-Input, CMOS, PDSO6
74LVC1G11GW	NXP	获取价格	Single 3-input AND gate
74LVC1G11GW	NEXPERIA	获取价格	Single 3-input AND gateProduction
74LVC1G11GW,125	NXP	获取价格	74LVC1G11 - Single 3-input AND gate TSSOP 6-Pin
74LVC1G11GWG	NXP	获取价格	LVC/LCX/Z SERIES, 3-INPUT AND GATE, PDSO6